sys/dev/pci/drm/i915/display/intel_display_device.c

1528

addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));

sys/dev/pci/drm/i915/display/intel_display_device.c

1547

val = bus_space_read_4(bst, bsh, i915_mmio_reg_offset(GMD_ID_DISPLAY));

sys/dev/pci/drm/i915/display/intel_dmc.c

1116

i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]),

sys/dev/pci/drm/i915/display/intel_dmc.c

1120

i+1, i915_mmio_reg_offset(dmc_info->mmioaddr[i+1]),

sys/dev/pci/drm/i915/display/intel_dmc.c

1126

i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i],

sys/dev/pci/drm/i915/display/intel_dmc.c

527

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/display/intel_dmc.c

528

u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0));

sys/dev/pci/drm/i915/display/intel_dmc.c

529

u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));

sys/dev/pci/drm/i915/display/intel_dmc.c

537

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/display/intel_dmc.c

538

u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0));

sys/dev/pci/drm/i915/display/intel_dmc.c

539

u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));

sys/dev/pci/drm/i915/display/intel_dmc.c

565

if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) !=

sys/dev/pci/drm/i915/display/intel_dmc.c

566

i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)))

sys/dev/pci/drm/i915/display/intel_dmc.c

681

dmc_id, i, i915_mmio_reg_offset(reg), expected, found);

sys/dev/pci/drm/i915/display/intel_dmc_wl.c

231

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/display/intel_dsb.c

304

return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/display/intel_dsb.c

349

i915_mmio_reg_offset(reg));

sys/dev/pci/drm/i915/display/intel_dsb.c

371

i915_mmio_reg_offset(reg));

sys/dev/pci/drm/i915/display/intel_dsb.c

389

i915_mmio_reg_offset(reg));

sys/dev/pci/drm/i915/display/intel_dsb.c

529

i915_mmio_reg_offset(reg));

sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c

2221

*cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

164

*cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));

sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c

204

*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);

sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c

926

*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

400

batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));

sys/dev/pci/drm/i915/gt/gen7_renderclear.c

406

batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

208

*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

216

*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;

sys/dev/pci/drm/i915/gt/gen8_engine_cs.c

501

*cs++ = i915_mmio_reg_offset(RING_PREDICATE_RESULT(0));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2758

*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

2760

*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3566

i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3568

i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));

sys/dev/pci/drm/i915/gt/intel_execlists_submission.c

3575

i915_mmio_reg_offset(RING_ELSP(base));

sys/dev/pci/drm/i915/gt/intel_gt_mcr.c

566

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1269

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1277

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1278

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1283

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1284

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1297

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1313

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1321

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1322

*cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0));

sys/dev/pci/drm/i915/gt/intel_lrc.c

1338

*cs++ = i915_mmio_reg_offset(DRAW_WATERMARK);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1348

*cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1645

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1651

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1660

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

sys/dev/pci/drm/i915/gt/intel_lrc.c

1727

*batch++ = i915_mmio_reg_offset(lri->reg);

sys/dev/pci/drm/i915/gt/intel_mocs.c

651

return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

709

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

713

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

718

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

723

*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

771

*cs++ = i915_mmio_reg_offset(

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

826

*cs++ = i915_mmio_reg_offset(last_reg);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

833

*cs++ = i915_mmio_reg_offset(last_reg);

sys/dev/pci/drm/i915/gt/intel_ring_submission.c

868

*cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1038

*cs++ = i915_mmio_reg_offset(wa->reg);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

148

unsigned int addr = i915_mmio_reg_offset(wa->reg);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1748

name, from, i915_mmio_reg_offset(wa->reg),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

177

if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

179

} else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {

sys/dev/pci/drm/i915/gt/intel_workarounds.c

187

i915_mmio_reg_offset(wa_->reg),

sys/dev/pci/drm/i915/gt/intel_workarounds.c

206

GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==

sys/dev/pci/drm/i915/gt/intel_workarounds.c

207

i915_mmio_reg_offset(wa_[1].reg));

sys/dev/pci/drm/i915/gt/intel_workarounds.c

208

if (i915_mmio_reg_offset(wa_[1].reg) >

sys/dev/pci/drm/i915/gt/intel_workarounds.c

209

i915_mmio_reg_offset(wa_[0].reg))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2179

i915_mmio_reg_offset(wa->reg));

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2185

i915_mmio_reg_offset(RING_NOPID(base)));

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3003

if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3012

u32 offset = i915_mmio_reg_offset(wa->reg);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

3092

if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))

sys/dev/pci/drm/i915/gt/selftest_execlists.c

1088

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

1597

*cs++ = i915_mmio_reg_offset(RING_START(0));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

305

i915_mmio_reg_offset(RING_START(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

310

i915_mmio_reg_offset(RING_CTL(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

315

i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

320

i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

325

i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

330

i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

335

i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

340

i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

345

i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

350

i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

355

i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

360

i915_mmio_reg_offset(RING_CMD_BUF_CCTL(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

365

i915_mmio_reg_offset(RING_BB_OFFSET(engine->mmio_base)),

sys/dev/pci/drm/i915/gt/selftest_lrc.c

445

*cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

452

*cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

769

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base));

sys/dev/pci/drm/i915/gt/selftest_lrc.c

966

if (offset == i915_mmio_reg_offset(RING_PREDICATE_RESULT(0)))

sys/dev/pci/drm/i915/gt/selftest_mocs.c

152

u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));

sys/dev/pci/drm/i915/gt/selftest_mocs.c

197

u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));

sys/dev/pci/drm/i915/gt/selftest_rc6.c

178

*cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO);

sys/dev/pci/drm/i915/gt/selftest_rps.c

103

*cs++ = i915_mmio_reg_offset(CS_GPR(i));

sys/dev/pci/drm/i915/gt/selftest_rps.c

105

*cs++ = i915_mmio_reg_offset(CS_GPR(i)) + 4;

sys/dev/pci/drm/i915/gt/selftest_rps.c

110

*cs++ = i915_mmio_reg_offset(CS_GPR(INC));

sys/dev/pci/drm/i915/gt/selftest_rps.c

125

*cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));

sys/dev/pci/drm/i915/gt/selftest_rps.c

208

i915_mmio_reg_offset(BXT_RP_STATE_CAP),

sys/dev/pci/drm/i915/gt/selftest_rps.c

213

i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS),

sys/dev/pci/drm/i915/gt/selftest_timeline.c

782

const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1011

i915_mmio_reg_offset(reg), a);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

1043

if (i915_mmio_reg_offset(wa->reg) &

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

157

*cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

184

return i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

465

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

520

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

870

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

906

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

961

u32 offset = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

965

i915_mmio_reg_offset(tbl->reg) == offset)

sys/dev/pci/drm/i915/gt/selftest_workarounds.c

989

i915_mmio_reg_offset(reg), a, b);

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

201

guc->send_regs.base = i915_mmio_reg_offset(MEDIA_SOFT_SCRATCH(0));

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

204

guc->send_regs.base = i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

214

guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

352

i915_mmio_reg_offset(reg), \

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

378

return guc_mmio_reg_add(gt, regset, i915_mmio_reg_offset(reg), flags);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

433

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

434

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

435

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

436

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

437

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

438

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

439

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false);

sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c

266

ext->reg = _MMIO(i915_mmio_reg_offset(extlist->reg));

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

407

i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

410

i915_mmio_reg_offset(GUC_WOPCM_SIZE),

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1056

cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))

sys/dev/pci/drm/i915/gvt/cmd_parser.c

926

if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||

sys/dev/pci/drm/i915/gvt/cmd_parser.c

929

offset == i915_mmio_reg_offset(INSTPM)))

sys/dev/pci/drm/i915/gvt/cmd_parser.c

963

if (offset == i915_mmio_reg_offset(DERRMR) ||

sys/dev/pci/drm/i915/gvt/cmd_parser.c

964

offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {

sys/dev/pci/drm/i915/gvt/edid.c

387

if (offset == i915_mmio_reg_offset(PCH_GMBUS2))

sys/dev/pci/drm/i915/gvt/edid.c

389

else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))

sys/dev/pci/drm/i915/gvt/edid.c

417

if (offset == i915_mmio_reg_offset(PCH_GMBUS0))

sys/dev/pci/drm/i915/gvt/edid.c

419

else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))

sys/dev/pci/drm/i915/gvt/edid.c

421

else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))

sys/dev/pci/drm/i915/gvt/edid.c

423

else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))

sys/dev/pci/drm/i915/gvt/gvt.h

460

(*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))

sys/dev/pci/drm/i915/gvt/gvt.h

464

(*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))

sys/dev/pci/drm/i915/gvt/handlers.c

1097

if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))

sys/dev/pci/drm/i915/gvt/handlers.c

1099

else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) ||

sys/dev/pci/drm/i915/gvt/handlers.c

1100

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))

sys/dev/pci/drm/i915/gvt/handlers.c

1102

else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) ||

sys/dev/pci/drm/i915/gvt/handlers.c

1103

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))

sys/dev/pci/drm/i915/gvt/handlers.c

1105

else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) ||

sys/dev/pci/drm/i915/gvt/handlers.c

1106

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))

sys/dev/pci/drm/i915/gvt/handlers.c

1200

offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) {

sys/dev/pci/drm/i915/gvt/handlers.c

1204

offset != i915_mmio_reg_offset(port_index ?

sys/dev/pci/drm/i915/gvt/handlers.c

180

((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)

sys/dev/pci/drm/i915/gvt/handlers.c

183

(num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))

sys/dev/pci/drm/i915/gvt/handlers.c

1980

offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||

sys/dev/pci/drm/i915/gvt/handlers.c

1981

offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {

sys/dev/pci/drm/i915/gvt/handlers.c

2160

ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \

sys/dev/pci/drm/i915/gvt/handlers.c

2832

if (offset >= i915_mmio_reg_offset(block->offset) &&

sys/dev/pci/drm/i915/gvt/handlers.c

2833

offset < i915_mmio_reg_offset(block->offset) + block->size)

sys/dev/pci/drm/i915/gvt/handlers.c

2933

if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0)))

sys/dev/pci/drm/i915/gvt/handlers.c

2957

i915_mmio_reg_offset(gvt->mmio.mmio_block->offset));

sys/dev/pci/drm/i915/gvt/handlers.c

3057

if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)

sys/dev/pci/drm/i915/gvt/handlers.c

3061

ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data);

sys/dev/pci/drm/i915/gvt/handlers.c

799

reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {

sys/dev/pci/drm/i915/gvt/handlers.c

817

if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))

sys/dev/pci/drm/i915/gvt/handlers.c

896

u32 start = i915_mmio_reg_offset(_start);

sys/dev/pci/drm/i915/gvt/handlers.c

897

u32 next = i915_mmio_reg_offset(_next);

sys/dev/pci/drm/i915/gvt/handlers.c

898

u32 end = i915_mmio_reg_offset(_end);

sys/dev/pci/drm/i915/gvt/interrupt.c

174

if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)

sys/dev/pci/drm/i915/gvt/interrupt.c

352

regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))

sys/dev/pci/drm/i915/gvt/interrupt.c

354

regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));

sys/dev/pci/drm/i915/gvt/interrupt.c

381

u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);

sys/dev/pci/drm/i915/gvt/interrupt.c

387

i915_mmio_reg_offset(up_irq_info->reg_base));

sys/dev/pci/drm/i915/gvt/interrupt.c

389

i915_mmio_reg_offset(up_irq_info->reg_base));

sys/dev/pci/drm/i915/gvt/interrupt.c

470

reg_base = i915_mmio_reg_offset(info->reg_base);

sys/dev/pci/drm/i915/gvt/interrupt.c

528

if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &

sys/dev/pci/drm/i915/gvt/interrupt.c

539

reg_base = i915_mmio_reg_offset(info->reg_base);

sys/dev/pci/drm/i915/gvt/interrupt.c

545

if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))

sys/dev/pci/drm/i915/gvt/mmio_context.c

238

*cs++ = i915_mmio_reg_offset(mmio->reg);

sys/dev/pci/drm/i915/gvt/mmio_context.c

268

*cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));

sys/dev/pci/drm/i915/gvt/mmio_context.c

295

*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));

sys/dev/pci/drm/i915/gvt/mmio_context.c

551

i915_mmio_reg_offset(mmio->reg),

sys/dev/pci/drm/i915/gvt/scheduler.c

114

i915_mmio_reg_offset(GEN8_OACTXCONTROL);

sys/dev/pci/drm/i915/gvt/scheduler.c

274

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =

sys/dev/pci/drm/i915/gvt/scheduler.c

278

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =

sys/dev/pci/drm/i915/gvt/scheduler.c

282

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =

sys/dev/pci/drm/i915/gvt/scheduler.c

92

i915_mmio_reg_offset(EU_PERF_CNTL0),

sys/dev/pci/drm/i915/gvt/scheduler.c

93

i915_mmio_reg_offset(EU_PERF_CNTL1),

sys/dev/pci/drm/i915/gvt/scheduler.c

94

i915_mmio_reg_offset(EU_PERF_CNTL2),

sys/dev/pci/drm/i915/gvt/scheduler.c

95

i915_mmio_reg_offset(EU_PERF_CNTL3),

sys/dev/pci/drm/i915/gvt/scheduler.c

96

i915_mmio_reg_offset(EU_PERF_CNTL4),

sys/dev/pci/drm/i915/gvt/scheduler.c

97

i915_mmio_reg_offset(EU_PERF_CNTL5),

sys/dev/pci/drm/i915/gvt/scheduler.c

98

i915_mmio_reg_offset(EU_PERF_CNTL6),

sys/dev/pci/drm/i915/i915_cmd_parser.c

1132

int ret = addr - i915_mmio_reg_offset(table[mid].addr);

sys/dev/pci/drm/i915/i915_cmd_parser.c

847

u32 curr = i915_mmio_reg_offset(reg_table[i].addr);

sys/dev/pci/drm/i915/i915_debugfs.c

482

i915_mmio_reg_offset(wa->reg),

sys/dev/pci/drm/i915/i915_ioctl.c

55

u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);

sys/dev/pci/drm/i915/i915_irq.c

107

i915_mmio_reg_offset(reg), val);

sys/dev/pci/drm/i915/i915_perf.c

1348

*cs++ = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/i915_perf.c

1511

offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));

sys/dev/pci/drm/i915/i915_perf.c

1947

*cs++ = i915_mmio_reg_offset(reg) + 4 * d;

sys/dev/pci/drm/i915/i915_perf.c

2044

*cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;

sys/dev/pci/drm/i915/i915_perf.c

2047

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));

sys/dev/pci/drm/i915/i915_perf.c

2048

*cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));

sys/dev/pci/drm/i915/i915_perf.c

2062

*cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;

sys/dev/pci/drm/i915/i915_perf.c

2065

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));

sys/dev/pci/drm/i915/i915_perf.c

2066

*cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));

sys/dev/pci/drm/i915/i915_perf.c

2085

*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));

sys/dev/pci/drm/i915/i915_perf.c

2086

*cs++ = i915_mmio_reg_offset(mi_predicate_result);

sys/dev/pci/drm/i915/i915_perf.c

2110

*cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET));

sys/dev/pci/drm/i915/i915_perf.c

2112

*cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4;

sys/dev/pci/drm/i915/i915_perf.c

2128

*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));

sys/dev/pci/drm/i915/i915_perf.c

2129

*cs++ = i915_mmio_reg_offset(mi_predicate_result);

sys/dev/pci/drm/i915/i915_perf.c

2194

*cs++ = i915_mmio_reg_offset(reg_data[i].addr);

sys/dev/pci/drm/i915/i915_perf.c

2443

u32 mmio = i915_mmio_reg_offset(reg);

sys/dev/pci/drm/i915/i915_perf.c

2455

if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)

sys/dev/pci/drm/i915/i915_perf.c

2543

*cs++ = i915_mmio_reg_offset(flex->reg);

sys/dev/pci/drm/i915/i915_perf.c

4360

if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)

sys/dev/pci/drm/i915/i915_perf.c

4379

((addr) == i915_mmio_reg_offset(mmio))

sys/dev/pci/drm/i915/i915_query.c

214

unsafe_put_user(i915_mmio_reg_offset(kernel_regs[r].addr),

sys/dev/pci/drm/i915/i915_reg_defs.h

198

#define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))

sys/dev/pci/drm/i915/intel_device_info.c

355

ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),

sys/dev/pci/drm/i915/intel_device_info.c

363

ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

43

ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \

sys/dev/pci/drm/i915/intel_uncore.c

1804

i915_mmio_reg_offset(reg)))

sys/dev/pci/drm/i915/intel_uncore.c

1818

i915_mmio_reg_offset(reg));

sys/dev/pci/drm/i915/intel_uncore.c

1901

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/pci/drm/i915/intel_uncore.c

1958

return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg));

sys/dev/pci/drm/i915/intel_uncore.c

2007

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/pci/drm/i915/intel_uncore.c

2048

return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg));

sys/dev/pci/drm/i915/intel_uncore.c

2118

d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + uncore->gsi_offset;

sys/dev/pci/drm/i915/intel_uncore.c

2119

d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) + uncore->gsi_offset;

sys/dev/pci/drm/i915/intel_uncore.h

330

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/pci/drm/i915/intel_uncore.h

340

u32 offset = i915_mmio_reg_offset(reg); \

sys/dev/pci/drm/i915/intel_uncore.h

520

readl(base + i915_mmio_reg_offset(reg))

sys/dev/pci/drm/i915/intel_uncore.h

522

writel(value, base + i915_mmio_reg_offset(reg))

sys/dev/pci/drm/i915/selftests/i915_perf.c

307

gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0));

sys/dev/pci/drm/i915/selftests/i915_request.c

1962

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP((ce->engine->mmio_base)));