i915_ggtt_offset
return i915_ggtt_offset(dsb_buf->vma);
plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma) +
i915_ggtt_offset(vma));
(unsigned long)(ggtt->gmadr.start + i915_ggtt_offset(vma));
addr_in = i915_ggtt_offset(gsc_context->vma);
overlay->flip_addr = i915_ggtt_offset(vma);
iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y);
iowrite32(i915_ggtt_offset(vma) + params->offset_U,
iowrite32(i915_ggtt_offset(vma) + params->offset_V,
i915_ggtt_offset(vma), plane_config->base);
plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma);
cache->node.start = i915_ggtt_offset(vma);
*pfn = (gmadr_start + i915_ggtt_offset(vma)) >> PAGE_SHIFT;
pfn = (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT;
if (!IS_ALIGNED(i915_ggtt_offset(vma), alignment))
*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
*cs++ = i915_ggtt_offset(vma) + offset;
*cs++ = i915_ggtt_offset(vma) + offset;
return (i915_ggtt_offset(engine->status_page.vma) +
return i915_ggtt_offset(rq->context->state) +
i915_ggtt_offset(ce->ring->vma),
offset = i915_ggtt_offset(ce->state) +
i915_ggtt_offset(rq->ring->vma),
i915_ggtt_offset(rq->ring->vma));
i915_ggtt_offset(rq->ring->vma),
i915_ggtt_offset(engine->status_page.vma));
fence->start = i915_ggtt_offset(vma);
return i915_ggtt_offset(gt->scratch) + field;
return i915_ggtt_offset(ce->state) + context_wa_bb_offset(ce);
*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +
*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +
*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +
return i915_ggtt_offset(ce->state) | desc;
regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) {
i915_ggtt_offset(ring->vma));
regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
i915_ggtt_offset(wa_ctx->vma) +
so->batch_offset = i915_ggtt_offset(so->vma);
set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));
ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma));
i915_ggtt_offset(ring->vma));
*cs++ = i915_ggtt_offset(engine->kernel_context->state) |
*cs++ = i915_ggtt_offset(ce->state) | flags;
i915_ggtt_offset(tl->hwsp_ggtt) +
tl->hwsp_offset = i915_ggtt_offset(tl->hwsp_ggtt) + next_ofs;
*hwsp = i915_ggtt_offset(tl->hwsp_ggtt) +
*cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
i915_ggtt_offset(ce->engine->status_page.vma) +
*cs++ = i915_ggtt_offset(vma);
*cs++ = i915_ggtt_offset(vma);
*cs++ = i915_ggtt_offset(vma);
*cs++ = i915_ggtt_offset(global);
*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
*cs++ = i915_ggtt_offset(vma) + 4 * idx;
*cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1);
*cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1);
*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
*cs++ = i915_ggtt_offset(ce->state) +
*cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32);
expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma);
*cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);
i915_ggtt_offset(ce->engine->status_page.vma) +
*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
i915_ggtt_offset(ce->engine->status_page.vma) +
i915_ggtt_offset(ce->engine->status_page.vma) +
offset = i915_ggtt_offset(vma);
offset -= i915_ggtt_offset(vma);
w->addr = i915_ggtt_offset(vma);
w->addr = i915_ggtt_offset(w->vma);
GEM_BUG_ON(w->addr - i915_ggtt_offset(w->vma) > w->vma->size);
end = (w->addr - i915_ggtt_offset(w->vma)) / sizeof(*w->map);
*cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
u32 offset = i915_ggtt_offset(gsc->local);
offset = i915_ggtt_offset(vma);
u64 addr_in = i915_ggtt_offset(gsc->proxy.vma);
u32 offset = i915_ggtt_offset(vma);
desc->process_desc = i915_ggtt_offset(ce->state) +
desc->wq_addr = i915_ggtt_offset(ce->state) +
wq_desc_offset = (u64)i915_ggtt_offset(ce->state) +
wq_base_offset = (u64)i915_ggtt_offset(ce->state) +
if (i915_ggtt_offset(ce->state) !=
i915_ggtt_offset(engine->status_page.vma));
return i915_ggtt_offset(ce->state) +
return i915_ggtt_offset(ce->state) +
pkt_offset = i915_ggtt_offset(huc->heci_pkt);
gma_start = i915_ggtt_offset(ce->state) + LRC_STATE_PN*PAGE_SIZE;
bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
node->start = i915_ggtt_offset(vma);
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
i915_ggtt_offset(scratch));
stream->specific_ctx_id = i915_ggtt_offset(ce->state);
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
*cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;
*cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
*cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
*cs++ = i915_ggtt_offset(stream->noa_wait);
offset = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
return ring == i915_ggtt_offset(rq->ring->vma);
mappable = i915_ggtt_offset(vma) + vma->fence_size <=
i915_ggtt_offset(stream->noa_wait), 0,
i915_ggtt_offset(stream->noa_wait), 0,
*cs++ = i915_ggtt_offset(rq->engine->status_page.vma) +
return (i915_ggtt_offset(ce->engine->status_page.vma) +
i915_ggtt_offset(engine->status_page.vma) +