sys/dev/pci/drm/amd/display/dc/core/dc.c

2484

mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc.c

4249

pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4340

cur_pipe->plane_res.hubp->funcs->validate_dml_output(

sys/dev/pci/drm/amd/display/dc/core/dc.c

4341

cur_pipe->plane_res.hubp, dc->ctx,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5680

struct hubp *hubp;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5695

hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5696

hubp->funcs->set_blank_regs(hubp, true);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5710

hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5711

hubp->funcs->set_blank_regs(hubp, false);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1222

struct hubp *hubp;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1240

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1241

if (!hubp)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1244

mpcc_inst = hubp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

850

block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

856

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2542

split_pipe->plane_res.hubp = pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3692

pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3837

pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5461

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

379

(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

464

pipe_ctx->plane_res.hubp->mpcc_id);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

765

struct hubp *hubp;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

785

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

786

if (hubp == NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

795

if (hubp->funcs->dmdata_set_attributes != NULL &&

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

797

hubp->funcs->dmdata_set_attributes(hubp, attr);

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

76

if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)

sys/dev/pci/drm/amd/display/dc/core/dc_surface.c

77

pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1030

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1033

if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1040

payload->cursor_rect.x = hubp->cur_rect.x;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1041

payload->cursor_rect.y = hubp->cur_rect.y;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1043

payload->cursor_rect.width = hubp->cur_rect.w;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1044

payload->cursor_rect.height = hubp->cur_rect.h;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1046

payload->enable = hubp->pos.cur_ctl.bits.cur_enable;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1054

const struct hubp *hubp, const struct dpp *dpp)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1057

pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1058

pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1059

pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1060

pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1069

const struct hubp *hubp, const struct dpp *dpp)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1072

pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1073

pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1074

pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1075

pl_A->aHubp.size.raw = hubp->att.size.raw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1076

pl_A->aHubp.settings.raw = hubp->att.settings.raw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1124

pCtx->plane_res.hubp, pCtx->plane_res.dpp);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1134

pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

427

fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

432

fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

849

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

851

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

135

struct hubp *hubp = pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

136

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

138

hubp->funcs->hubp_read_state(hubp);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

145

hubp->inst,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

164

hubp->inst,

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

514

struct hubp *hubp = pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

515

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

517

hubp->funcs->hubp_read_state(hubp);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

520

hubp->funcs->hubp_clear_underflow(hubp);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

537

secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1888

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

276

if (existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

277

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

316

if ((existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

317

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) ||

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

103

void hubp1_clear_underflow(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

105

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1092

void hubp1_read_state(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1094

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1098

hubp1_read_state_common(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

110

static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

112

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1166

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1169

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1174

hubp->curs_attr = *attr;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

118

void hubp1_vready_workaround(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1198

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1202

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1209

int cursor_height = (int)hubp->curs_attr.height;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1210

int cursor_width = (int)hubp->curs_attr.width;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1214

hubp->curs_pos = *pos;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

122

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1223

if (hubp->curs_attr.address.quad_part == 0)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1272

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1298

void hubp1_clk_cntl(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1300

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1306

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1308

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1313

bool hubp1_in_blank(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1316

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1322

void hubp1_soft_reset(struct hubp *hubp, bool reset)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1324

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1334

void hubp1_set_flip_int(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1336

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1349

static void hubp1_wait_pipe_read_start(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1351

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1358

void hubp1_init(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1360

hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

142

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

146

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

164

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

169

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

204

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

208

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

237

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

240

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

350

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

354

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

41

void hubp1_set_blank(struct hubp *hubp, bool blank)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

43

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

516

hubp->request_address = *address;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

521

void hubp1_clear_tiling(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

523

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

535

void hubp1_dcc_control(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

540

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

549

void hubp_reset(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

551

memset(&hubp->pos, 0, sizeof(hubp->pos));

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

552

memset(&hubp->att, 0, sizeof(hubp->att));

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

556

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

565

hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

566

hubp1_program_tiling(hubp, tiling_info, format);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

567

hubp1_program_size(hubp, format, plane_size, dcc);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

568

hubp1_program_rotation(hubp, rotation, horizontal_mirror);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

569

hubp1_program_pixel_format(hubp, format);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

573

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

576

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

607

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

611

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

65

hubp->mpcc_id = 0xf;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

66

hubp->opp_id = OPP_ID_INVALID;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

695

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

70

static void hubp1_disconnect(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

704

hubp1_program_requestor(hubp, rq_regs);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

705

hubp1_program_deadline(hubp, dlg_attr, ttu_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

706

hubp1_vready_workaround(hubp, pipe_dest);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

710

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

714

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

72

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

751

bool hubp1_is_flip_pending(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

754

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

757

if (hubp && hubp->power_gated)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

772

if (hubp &&

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

773

earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

782

static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

785

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

81

static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

811

static void hubp1_set_vm_context0_settings(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

814

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

83

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

847

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

851

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

888

void hubp1_read_state_common(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

890

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

90

static unsigned int hubp1_get_underflow_status(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

93

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

30

#define TO_DCN10_HUBP(hubp)\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

31

container_of(hubp, struct dcn10_hubp, base)

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

723

struct hubp base;

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

731

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

741

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

746

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

750

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

754

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

760

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

765

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

769

void hubp1_dcc_control(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

773

void hubp_reset(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

776

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

780

bool hubp1_is_flip_pending(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

783

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

787

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

791

void hubp1_set_blank(struct hubp *hubp, bool blank);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

793

void min_set_viewport(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

797

void hubp1_clk_cntl(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

798

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

808

void hubp1_read_state(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

809

void hubp1_clear_underflow(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

813

void hubp1_vready_workaround(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

816

void hubp1_init(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

817

void hubp1_read_state_common(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

818

bool hubp1_in_blank(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

819

void hubp1_soft_reset(struct hubp *hubp, bool reset);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

821

void hubp1_set_flip_int(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

823

void hubp1_clear_tiling(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1000

int cursor_width = (int)hubp->curs_attr.width;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1004

hubp->curs_pos = *pos;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1013

if (hubp->curs_attr.address.quad_part == 0)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1061

if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1063

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1081

hubp->pos.cur_ctl.bits.cur_enable = cur_en;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1082

hubp->pos.position.bits.x_pos = pos->x;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1083

hubp->pos.position.bits.y_pos = pos->y;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1084

hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1085

hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1086

hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1099

hubp->cur_rect.x = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1100

hubp->cur_rect.y = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1101

hubp->cur_rect.w = param->stream->timing.h_addressable;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1102

hubp->cur_rect.h = param->stream->timing.v_addressable;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1104

hubp->cur_rect.x = src_x_offset + param->viewport.x;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1105

hubp->cur_rect.y = src_y_offset + param->viewport.y;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1109

void hubp2_clk_cntl(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1111

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1117

void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1119

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1124

void hubp2_clear_underflow(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1126

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1131

void hubp2_read_state_common(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1133

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1323

void hubp2_read_state(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1325

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1329

hubp2_read_state_common(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1359

static void hubp2_validate_dml_output(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1365

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

172

void hubp2_vready_at_or_After_vsync(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

176

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

197

static void hubp2_program_requestor(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

200

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

230

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

240

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

241

hubp2_program_requestor(hubp, rq_regs);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

242

hubp2_program_deadline(hubp, dlg_attr, ttu_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

247

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

251

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

329

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

334

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

377

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

381

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

409

void hubp2_clear_tiling(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

411

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

423

void hubp2_dcc_control(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

428

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

438

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

441

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

47

void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

50

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

551

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

560

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

562

hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

564

hubp2_program_size(hubp, format, plane_size, dcc);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

565

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

566

hubp2_program_pixel_format(hubp, format);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

606

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

609

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

614

hubp->curs_attr = *attr;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

637

hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

638

hubp->att.SURFACE_ADDR = attr->address.low_part;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

639

hubp->att.size.bits.width = attr->width;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

640

hubp->att.size.bits.height = attr->height;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

641

hubp->att.cur_ctl.bits.mode = attr->color_format;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

643

hubp->cur_rect.w = attr->width;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

644

hubp->cur_rect.h = attr->height;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

646

hubp->att.cur_ctl.bits.pitch = hw_pitch;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

647

hubp->att.cur_ctl.bits.line_per_chunk = lpc;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

648

hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

649

hubp->att.settings.bits.dst_y_offset = 0;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

650

hubp->att.settings.bits.chunk_hdl_adjust = 3;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

654

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

657

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

694

hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

705

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

710

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

717

bool hubp2_dmdata_status_done(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

720

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

727

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

731

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

82

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

86

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

884

hubp->request_address = *address;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

890

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

893

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

906

struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

908

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

916

void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

918

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

923

bool hubp2_is_flip_pending(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

926

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

929

if (hubp && hubp->power_gated)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

944

if (hubp &&

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

945

earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

951

void hubp2_set_blank(struct hubp *hubp, bool blank)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

953

hubp2_set_blank_regs(hubp, blank);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

956

hubp->mpcc_id = 0xf;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

957

hubp->opp_id = OPP_ID_INVALID;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

961

void hubp2_set_blank_regs(struct hubp *hubp, bool blank)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

963

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

988

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

992

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

999

int cursor_height = (int)hubp->curs_attr.height;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

300

struct hubp base;

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

31

#define TO_DCN20_HUBP(hubp)\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

316

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

32

container_of(hubp, struct dcn20_hubp, base)

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

320

void hubp2_vready_at_or_After_vsync(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

324

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

327

void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

335

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

339

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

343

bool hubp2_dmdata_status_done(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

346

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

350

struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

352

void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

355

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

360

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

364

void hubp2_dcc_control(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

368

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

374

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

379

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

383

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

392

bool hubp2_is_flip_pending(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

394

void hubp2_set_blank(struct hubp *hubp, bool blank);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

395

void hubp2_set_blank_regs(struct hubp *hubp, bool blank);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

398

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

402

void hubp2_clk_cntl(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

404

void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

406

void hubp2_clear_underflow(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

408

void hubp2_read_state_common(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

410

void hubp2_read_state(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

412

void hubp2_clear_tiling(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

107

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

108

hubp201_program_requestor(hubp, rq_regs);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

109

hubp201_program_deadline(hubp, dlg_attr, ttu_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

43

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

52

hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

53

hubp1_program_tiling(hubp, tiling_info, format);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

54

hubp1_program_size(hubp, format, plane_size, dcc);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

55

hubp1_program_pixel_format(hubp, format);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

59

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

63

hubp1_program_deadline(hubp, dlg_attr, ttu_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

66

static void hubp201_program_requestor(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

69

struct dcn201_hubp *hubp201 = TO_DCN201_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

97

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

117

struct hubp base;

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

32

#define TO_DCN201_HUBP(hubp)\

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

33

container_of(hubp, struct dcn201_hubp, base)

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

130

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

134

hubp2_program_deadline(hubp, dlg_attr, ttu_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

136

apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

140

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

143

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

172

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

182

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

183

hubp21_program_requestor(hubp, rq_regs);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

184

hubp21_program_deadline(hubp, dlg_attr, ttu_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

189

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

193

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

230

static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

233

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

253

static void hubp21_validate_dml_output(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

259

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

596

static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs)

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

598

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

669

static void dmcub_PLAT_54186_wa(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

672

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

688

cmd.PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

694

dc_wake_and_execute_dmub_cmd(hubp->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

699

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

796

if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

797

dmcub_PLAT_54186_wa(hubp, &flip_regs);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

799

program_surface_flip_and_addr(hubp, &flip_regs);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

80

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

801

hubp->request_address = *address;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

806

static void hubp21_init(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

811

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

815

hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

83

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

106

struct hubp base;

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

123

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

127

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

132

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

32

#define TO_DCN21_HUBP(hubp)\

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

33

container_of(hubp, struct dcn21_hubp, base)

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

314

hubp->request_address = *address;

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

337

void hubp3_clear_tiling(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

339

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

353

void hubp3_dcc_control(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

357

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

366

void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

369

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

381

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

384

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

412

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

421

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

423

hubp3_dcc_control_sienna_cichlid(hubp, dcc);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

425

hubp2_program_size(hubp, format, plane_size, dcc);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

426

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

427

hubp2_program_pixel_format(hubp, format);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

431

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

435

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

437

hubp2_program_deadline(hubp, dlg_attr, ttu_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

442

void hubp3_read_state(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

444

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

448

hubp2_read_state_common(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

45

void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

48

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

480

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

489

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

490

hubp21_program_requestor(hubp, rq_regs);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

491

hubp3_program_deadline(hubp, dlg_attr, ttu_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

494

void hubp3_init(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

499

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

505

hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

508

uint32_t hubp3_get_current_read_line(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

511

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

520

unsigned int hubp3_get_underflow_status(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

523

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

69

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

73

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

257

void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

261

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

266

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

276

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

287

void hubp3_dcc_control(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

290

void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

294

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

297

void hubp3_read_state(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

299

void hubp3_init(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

301

void hubp3_clear_tiling(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

303

uint32_t hubp3_get_current_read_line(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

305

uint32_t hubp3_get_underflow_status(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

42

void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

44

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

50

void hubp31_soft_reset(struct hubp *hubp, bool reset)

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

52

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

57

static void hubp31_program_extended_blank(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

60

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

66

struct hubp *hubp, unsigned int min_dst_y_next_start_optimized)

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

68

hubp31_program_extended_blank(hubp, min_dst_y_next_start_optimized);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

71

uint32_t hubp31_get_det_config_error(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

74

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

244

void hubp31_soft_reset(struct hubp *hubp, bool reset);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

246

void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

249

struct hubp *hubp, unsigned int min_dst_y_next_start_optimized);

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

251

uint32_t hubp31_get_det_config_error(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

109

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

112

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

122

hubp->curs_attr = *attr;

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

167

void hubp32_init(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

169

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

42

void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow)

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

44

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

50

void hubp32_update_force_cursor_pstate_disallow(struct hubp *hubp, bool pstate_disallow)

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

52

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

59

void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

61

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

68

void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

70

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

86

void hubp32_phantom_hubp_post_enable(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

89

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

47

void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

49

void hubp32_update_force_cursor_pstate_disallow(struct hubp *hubp, bool pstate_disallow);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

51

void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

53

void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

55

void hubp32_phantom_hubp_post_enable(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

57

void hubp32_cursor_set_attributes(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

60

void hubp32_init(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

173

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

182

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

184

hubp3_dcc_control_sienna_cichlid(hubp, dcc);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

186

hubp2_program_size(hubp, format, plane_size, dcc);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

187

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

188

hubp35_program_pixel_format(hubp, format);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

41

void hubp35_set_fgcg(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

43

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

48

void hubp35_init(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

50

hubp3_init(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

52

hubp35_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

58

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

61

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

59

void hubp35_set_fgcg(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

62

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

66

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

75

void hubp35_init(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

101

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1014

void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1016

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

109

void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

111

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

116

void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

118

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

123

void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

125

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

131

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

134

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

167

void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

169

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

179

void hubp401_init(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

181

hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

184

void hubp401_vready_at_or_After_vsync(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

198

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

221

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

224

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

249

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

253

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

347

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

355

hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

356

hubp401_program_requestor(hubp, &pipe_regs->rq_regs);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

357

hubp401_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

361

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

364

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

410

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

414

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

43

void hubp401_program_3dlut_fl_addr(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

46

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

52

void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

54

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

555

hubp->request_address = *address;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

560

void hubp401_clear_tiling(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

562

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

572

void hubp401_dcc_control(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

575

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

59

void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

596

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

601

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

61

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

630

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

639

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

641

hubp401_dcc_control(hubp, dcc);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

643

hubp401_program_size(hubp, format, plane_size, dcc);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

644

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

645

hubp2_program_pixel_format(hubp, format);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

649

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

653

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

66

int hubp401_get_3dlut_fl_done(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

68

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

691

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

694

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

710

void hubp401_set_flip_int(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

712

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

720

bool hubp401_in_blank(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

722

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

731

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

735

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

745

hubp->curs_pos = *pos;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

75

void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

762

if (hubp->curs_attr.address.quad_part == 0)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

77

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

770

(1 + hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

782

if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

784

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

802

hubp->pos.cur_ctl.bits.cur_enable = cur_en;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

803

hubp->pos.position.bits.x_pos = pos->x;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

804

hubp->pos.position.bits.y_pos = pos->y;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

805

hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

806

hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

807

hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

818

hubp->cur_rect.x = rec_x_offset + param->recout.x;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

819

hubp->cur_rect.y = rec_y_offset + param->recout.y;

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

82

void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

822

void hubp401_read_state(struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

824

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

84

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

89

void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

91

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

96

void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

259

void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

262

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

268

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

272

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

276

void hubp401_dcc_control(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

285

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

291

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

300

void hubp401_set_viewport(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

304

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

306

void hubp401_set_flip_int(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

308

bool hubp401_in_blank(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

311

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

315

void hubp401_read_state(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

325

void hubp401_init(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

327

int hubp401_get_3dlut_fl_done(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

329

void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

331

void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

333

void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

338

void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

340

void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

342

void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

344

void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

346

void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

348

void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address address);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

350

void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

352

void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

355

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

358

void hubp401_clear_tiling(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

360

void hubp401_vready_at_or_After_vsync(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

365

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

369

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1036

struct hubp *hubp = dc->res_pool->hubps[0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1041

hubp->funcs->set_blank(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1056

struct hubp *hubp = dc->res_pool->hubps[0];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1079

hubp->funcs->set_hubp_blank_en(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1351

struct hubp *hubp ;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1370

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1372

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1373

hubp->funcs->set_hubp_blank_en(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1383

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1385

if (hubp != NULL && hubp->funcs->hubp_disable_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1386

hubp->funcs->hubp_disable_control(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1393

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1395

if (hubp != NULL && hubp->funcs->hubp_disable_control)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1396

hubp->funcs->hubp_disable_control(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1405

hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1407

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1408

hubp->funcs->set_hubp_blank_en(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1445

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1467

if (hubp->funcs->hubp_disconnect)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1468

hubp->funcs->hubp_disconnect(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1489

struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1502

hws->funcs.hubp_pg_control(hws, hubp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1504

hubp->funcs->hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1510

"Power gated front end %d\n", hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1523

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1525

int opp_id = hubp->opp_id;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1529

hubp->funcs->hubp_clk_cntl(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1538

hubp->power_gated = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1543

pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1558

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1613

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1619

if (hubbub && hubp) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1621

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1623

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1641

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1658

hubp->power_gated = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1666

hubp->funcs->hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1672

pipe_ctx->plane_res.hubp = hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1675

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1676

hubp->opp_id = OPP_ID_INVALID;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1677

hubp->power_gated = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1692

pipe_ctx->plane_res.hubp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2017

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2018

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2717

static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2719

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2726

hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2727

hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2744

pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2747

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2755

dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2764

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2765

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2889

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2931

mpcc_id = hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2956

hubp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2961

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2962

hubp->mpcc_id = mpcc_id;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2983

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

303

struct hubp *hubp = pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

304

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3050

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3052

hubp->funcs->hubp_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3053

hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3058

hubp->funcs->hubp_setup_interdependent(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3059

hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

306

hubp->funcs->hubp_read_state(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3086

hubp->funcs->mem_program_viewport(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3087

hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

310

hubp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3120

hubp->funcs->hubp_program_surface_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3121

hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3131

hubp->power_gated = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3136

hubp->funcs->set_blank(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3543

static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3572

struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3578

hubp->funcs->set_blank(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3607

flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3608

pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3646

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3859

hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3860

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3867

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3868

pipe_ctx->plane_res.hubp, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4107

struct hubp *hubp = pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4108

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4110

hubp->funcs->hubp_read_state(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4131

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4133

if (!hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4137

if (clear_tiling && hubp->funcs->hubp_clear_tiling)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4138

hubp->funcs->hubp_clear_tiling(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4141

hubp->funcs->hubp_program_surface_flip_and_addr(hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

815

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

823

if (hubp->funcs->hubp_get_underflow_status(hubp)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

824

hubp->funcs->hubp_clear_underflow(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

200

struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1009

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1032

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1301

hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1308

"Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1321

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1324

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1377

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1383

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1384

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1426

if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1685

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1704

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1706

if (hubp->funcs->hubp_setup2) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1707

hubp->funcs->hubp_setup2(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1708

hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1713

hubp->funcs->hubp_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1714

hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1722

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1723

hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1726

if (hubp->funcs->hubp_setup_interdependent2) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1727

hubp->funcs->hubp_setup_interdependent2(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1728

hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1731

hubp->funcs->hubp_setup_interdependent(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1732

hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1790

hubp->funcs->mem_program_viewport(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1791

hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1797

if (hubp->funcs->hubp_program_mcache_id_and_split_coordinate)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1798

hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, &pipe_ctx->mcache_regs);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1826

hubp->opp_id);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1843

hubp->funcs->hubp_program_surface_config(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1844

hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1852

hubp->power_gated = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1871

hubp->funcs->set_blank(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1873

if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1874

hubp->funcs->phantom_hubp_post_enable(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1965

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1969

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2137

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2140

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2199

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2202

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2275

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2279

&& hubp->funcs->hubp_is_flip_pending(hubp); j++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2475

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2478

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2526

pipe_ctx->plane_res.hubp->funcs->hubp_setup(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2527

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2604

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2606

if (!hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2608

return hubp->funcs->dmdata_status_done(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2644

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2658

hubp->funcs->dmdata_set_attributes(hubp, &attr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2741

vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2743

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2744

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2935

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2982

mpcc_id = hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3008

hubp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

301

if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3013

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3014

hubp->mpcc_id = mpcc_id;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

302

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

303

pipe_ctx->plane_res.hubp, flip_immediate);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3108

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3121

if (!hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3128

hubp->inst, mode);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3197

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3203

pipe_ctx->plane_res.hubp = hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3206

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3207

hubp->opp_id = OPP_ID_INVALID;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3208

hubp->power_gated = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3211

hubp->funcs->hubp_init(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3238

pipe_ctx->plane_res.hubp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

397

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

398

pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

399

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

713

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

724

if (hubp->funcs->hubp_update_mall_sel)

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

725

hubp->funcs->hubp_update_mall_sel(hubp, 0, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

729

hubp->funcs->hubp_clk_cntl(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

733

hubp->power_gated = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

737

pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

757

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

149

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

150

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

307

struct hubp *hubp = res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

313

pipe_ctx->plane_res.hubp = hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

316

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

317

hubp->opp_id = OPP_ID_INVALID;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

318

hubp->power_gated = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

321

hubp->funcs->hubp_init(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

346

pipe_ctx->plane_res.hubp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

380

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

415

if (hubp->funcs->hubp_disconnect)

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

416

hubp->funcs->hubp_disconnect(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

424

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

481

dpp_id = hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

521

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

522

hubp->mpcc_id = mpcc_id;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

562

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

563

pipe_ctx->plane_res.hubp, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

571

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

588

hubp->funcs->dmdata_set_attributes(hubp, &attr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1256

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1258

if (hubp) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1259

if (hubp->funcs->hubp_get_underflow_status)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1260

out_data->hubps[i].hubp_underflow = hubp->funcs->hubp_get_underflow_status(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1262

if (hubp->funcs->hubp_in_blank)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1263

out_data->hubps[i].hubp_in_blank = hubp->funcs->hubp_in_blank(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1265

if (hubp->funcs->hubp_get_current_read_line)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1266

out_data->hubps[i].hubp_readline = hubp->funcs->hubp_get_current_read_line(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1268

if (hubp->funcs->hubp_get_det_config_error)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1269

out_data->hubps[i].det_config_error = hubp->funcs->hubp_get_det_config_error(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

257

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

359

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

395

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

886

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

899

if (!hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

906

hubp->inst, mode);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

641

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

644

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

443

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

480

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

566

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

610

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

618

if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

619

hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

620

if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

621

hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

630

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

655

if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

656

hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

657

if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

658

hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

675

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

677

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

678

int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

680

switch (hubp->curs_attr.color_format) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

701

hubp->funcs->hubp_update_mall_sel(hubp, 1, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

704

hubp->funcs->hubp_update_mall_sel(hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

735

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

737

if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

744

hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1047

if (j == PG_HUBP && new_pipe->plane_res.hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1048

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1073

cur_pipe->plane_res.hubp != new_pipe->plane_res.hubp &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1074

new_pipe->plane_res.hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1075

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1133

if (new_pipe->plane_res.hubp &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1134

new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

665

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

671

if (hubbub && hubp) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

673

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

675

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

693

struct hubp *hubp = dc->res_pool->hubps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

710

hubp->power_gated = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

718

hubp->funcs->hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

724

pipe_ctx->plane_res.hubp = hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

727

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

728

hubp->opp_id = OPP_ID_INVALID;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

729

hubp->power_gated = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

744

pipe_ctx->plane_res.hubp = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

823

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

826

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

844

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

851

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

852

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

860

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

878

hubp->funcs->hubp_clk_cntl(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

883

hubp->power_gated = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

885

hubp->funcs->hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

906

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

955

if (pipe_ctx->plane_res.hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

956

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

958

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

959

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

971

if (!pipe_ctx->top_pipe && pipe_ctx->plane_res.hubp &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

972

pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1076

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1171

if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1172

adjust_hotspot_between_slices_for_2x_magnify(hubp->curs_attr.width, &pos_cpy);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1192

if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1193

adjust_hotspot_between_slices_for_2x_magnify(hubp->curs_attr.width, &pos_cpy);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1215

if (recout_x_pos + (int)hubp->curs_attr.width <= 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1218

if (recout_y_pos + (int)hubp->curs_attr.height <= 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1221

hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1222

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1469

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1472

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1686

dpp_pipe->plane_res.hubp &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1688

hubbub->funcs->wait_for_det_update(hubbub, dpp_pipe->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1691

if (hubbub && opp_heads[slice_idx]->plane_res.hubp && hubbub->funcs->wait_for_det_update)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1692

hubbub->funcs->wait_for_det_update(hubbub, opp_heads[slice_idx]->plane_res.hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1781

if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1782

wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1790

if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1791

wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2020

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2023

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2194

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2197

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2256

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2259

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2297

struct hubp *hubp = pipe->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2301

&& hubp->funcs->hubp_is_flip_pending(hubp); j++)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2441

if (pipe_ctx->plane_res.hubp->funcs->hubp_setup2)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2442

pipe_ctx->plane_res.hubp->funcs->hubp_setup2(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2443

pipe_ctx->plane_res.hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2651

struct hubp *hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2669

hws->funcs.hubp_pg_control(hws, hubp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2671

hubp->funcs->hubp_reset(hubp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2679

"Power gated front end %d\n", hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

380

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

411

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

412

int mpcc_id = hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

473

if (hubp->funcs->hubp_enable_3dlut_fl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

474

hubp->funcs->hubp_enable_3dlut_fl(hubp, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

508

if (hubp->funcs->hubp_program_3dlut_fl_addr)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

509

hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

532

if (hubp->funcs->hubp_program_3dlut_fl_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

533

hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

535

if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

536

hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

549

if (hubp->funcs->hubp_program_3dlut_fl_format)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

550

hubp->funcs->hubp_program_3dlut_fl_format(hubp, format);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

551

if (hubp->funcs->hubp_update_3dlut_fl_bias_scale &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

557

hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

573

if (hubp->funcs->hubp_program_3dlut_fl_crossbar)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

574

hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

586

mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

588

if (hubp->funcs->hubp_enable_3dlut_fl)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

589

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

604

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

606

if (hubp->funcs->hubp_enable_3dlut_fl) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

607

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

615

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

668

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

111

struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

114

struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

66

struct hubp;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

245

struct hubp *hubps[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

377

struct hubp *hubp;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

158

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

165

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

171

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

176

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

179

void (*dcc_control)(struct hubp *hubp, bool enable,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

182

void (*hubp_reset)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

185

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

190

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

195

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

201

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

205

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

209

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

218

bool (*hubp_is_flip_pending)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

220

void (*set_blank)(struct hubp *hubp, bool blank);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

221

void (*set_blank_regs)(struct hubp *hubp, bool blank);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

222

void (*phantom_hubp_post_enable)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

223

void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

226

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

230

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

234

void (*hubp_disconnect)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

236

void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

237

void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

238

void (*hubp_read_state)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

239

void (*hubp_clear_underflow)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

240

void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

241

unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

242

void (*hubp_init)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

245

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

249

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

252

bool (*dmdata_status_done)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

254

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

258

struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

261

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

265

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

271

struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

273

bool (*hubp_in_blank)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

274

void (*hubp_soft_reset)(struct hubp *hubp, bool reset);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

276

void (*hubp_set_flip_int)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

278

void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

279

void (*hubp_update_force_cursor_pstate_disallow)(struct hubp *hubp, bool allow);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

280

void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

281

void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

282

void (*hubp_surface_update_lock)(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

285

void (*program_extended_blank)(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

288

void (*hubp_wait_pipe_read_start)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

289

void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

290

void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

291

void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

293

void (*hubp_program_3dlut_fl_format)(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

295

void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

297

void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

298

void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

299

void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

300

void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

301

void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

302

void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp,

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

306

int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

307

void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

308

void (*hubp_clear_tiling)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

309

uint32_t (*hubp_get_current_read_line)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

310

uint32_t (*hubp_get_det_config_error)(struct hubp *hubp);

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1102

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

979

static struct hubp *dcn10_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1196

struct hubp *dcn20_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1491

next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1547

secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2164

sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

105

struct hubp *dcn20_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1021

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

981

static struct hubp *dcn201_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

977

static struct hubp *dcn21_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1196

static struct hubp *dcn30_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1534

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1158

static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

504

static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

485

static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1494

static struct hubp *dcn31_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1552

static struct hubp *dcn31_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1494

static struct hubp *dcn31_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1487

static struct hubp *dcn31_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2763

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2822

free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2854

free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

888

static struct hubp *dcn32_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

44

struct hubp *hubp = pipe_ctx->plane_res.hubp;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

45

uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

882

static struct hubp *dcn321_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1566

static struct hubp *dcn35_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1546

static struct hubp *dcn35_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1547

static struct hubp *dcn35_hubp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

881

static struct hubp *dcn401_hubp_create(