sys/dev/pci/drm/amd/display/dc/bios/command_table.c

1426

case CLOCK_SOURCE_ID_PLL0:

sys/dev/pci/drm/amd/display/dc/bios/command_table_helper.c

336

case CLOCK_SOURCE_ID_PLL0:

sys/dev/pci/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c

113

case CLOCK_SOURCE_ID_PLL0:

sys/dev/pci/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c

69

case CLOCK_SOURCE_ID_PLL0:

sys/dev/pci/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c

69

case CLOCK_SOURCE_ID_PLL0:

sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

251

pxl_clk_params.pll_id = CLOCK_SOURCE_ID_PLL0;

sys/dev/pci/drm/amd/display/dc/hwss/dce/dce_hwseq.c

194

uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1021

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

sys/dev/pci/drm/amd/display/dc/resource/dce100/dce100_resource.c

1030

dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce110/dce110_resource.c

1391

dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1122

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1131

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

1328

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce60/dce60_resource.c

933

dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1134

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

1143

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

934

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);

sys/dev/pci/drm/amd/display/dc/resource/dce80/dce80_resource.c

943

dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);