gvt_vgpu_err
gvt_vgpu_err("Failed to alloc fences\n");
gvt_vgpu_err("Invalid vGPU creation params\n");
gvt_vgpu_err("unknown plane code %d\n", plane);
gvt_vgpu_err("fail to decode MI display flip command\n");
gvt_vgpu_err("invalid MI display flip command\n");
gvt_vgpu_err("fail to update plane mmio\n");
gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
gvt_vgpu_err("command address audit fail name %s\n",
gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
gvt_vgpu_err("invalid gma address: %lx\n", gma);
gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
gvt_vgpu_err("fail to copy guest ring buffer\n");
gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
gvt_vgpu_err("invalid shadow batch buffer\n");
gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
gvt_vgpu_err("%s handler error\n", info->name);
gvt_vgpu_err("%s IP advance error\n", info->name);
gvt_vgpu_err("ip_gma %lx out of ring scope."
gvt_vgpu_err("ip_gma %lx out of range."
gvt_vgpu_err("cmd parser error\n");
gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
gvt_vgpu_err("fail to copy guest ring buffer\n");
gvt_vgpu_err("fail to copy guest ring buffer\n");
gvt_vgpu_err("fail to shadow workload ring_buffer\n");
gvt_vgpu_err("scan workload error\n");
gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
gvt_vgpu_err("fail to copy guest indirect ctx\n");
gvt_vgpu_err("fail to shadow indirect ctx\n");
gvt_vgpu_err("scan wa ctx error\n");
gvt_vgpu_err("scan shadow ctx error\n");
gvt_vgpu_err("failed to get the 4-level shadow vm\n");
gvt_vgpu_err("invalid shared shadow vm type\n");
gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
gvt_vgpu_err("%s access to non-render register (%x)\n",
gvt_vgpu_err("%s access to register (%x)\n",
gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
gvt_vgpu_err("try to write RO reg %x\n",
gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled);
gvt_vgpu_err("invalid plane id:%d\n", plane_id);
gvt_vgpu_err("fb size is zero\n");
gvt_vgpu_err("Not aligned fb address:0x%llx\n", info->start);
gvt_vgpu_err("invalid gma addr\n");
gvt_vgpu_err("alloc dmabuf_obj failed\n");
gvt_vgpu_err("allocate intel vgpu fb info failed\n");
gvt_vgpu_err("invalid dmabuf id:%d\n", dmabuf_id);
gvt_vgpu_err("create gvt gem obj failed\n");
gvt_vgpu_err("export dma-buf failed\n");
gvt_vgpu_err("create dma-buf fd failed ret:%d\n", ret);
gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
gvt_vgpu_err("warning: gmbus3 read with nothing returned\n");
gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");
gvt_vgpu_err("Reading EDID but EDID is not available!\n");
gvt_vgpu_err("No EDID available during the reading?\n");
gvt_vgpu_err("schedule out context is not running context,"
gvt_vgpu_err("virtual execlist slots are full\n");
gvt_vgpu_err("no available execlist slot\n");
gvt_vgpu_err("fail to emulate execlist schedule in\n");
gvt_vgpu_err("invalid elsp submission, desc0 is invalid\n");
gvt_vgpu_err("unexpected GGTT elsp submission\n");
gvt_vgpu_err("failed to submit desc %d\n", i);
gvt_vgpu_err("descriptors content: desc0 %08x %08x desc1 %08x %08x\n",
gvt_vgpu_err("Out-of-bounds pixel format index\n");
gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n",
gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
gvt_vgpu_err("GVT doesn't support 1GB entry\n");
gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
gvt_vgpu_err("fail to find guest page\n");
gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
gvt_vgpu_err("fail to populate guest root pointer\n");
gvt_vgpu_err("failed to shadow ppgtt mm\n");
gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm->type, gma);
gvt_vgpu_err("fail to populate guest ggtt entry\n");
gvt_vgpu_err("fail to allocate scratch page\n");
gvt_vgpu_err("fail to dmamap scratch_pt\n");
gvt_vgpu_err("fail to create mm for ggtt.\n");
gvt_vgpu_err("fail to create mm\n");
gvt_vgpu_err("fail to find ppgtt instance.\n");
gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
gvt_vgpu_err("fail to map dma addr\n");
gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
gvt_vgpu_err("Unsupported DP port access!\n");
gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
gvt_vgpu_err("SBI caching meets maximum limits\n");
gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
gvt_vgpu_err("Invalid PV notification %d\n", notification);
gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
gvt_vgpu_err("fail submit workload on ring %s\n",
gvt_vgpu_err("access oob fence reg %d/%d\n",
gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
gvt_vgpu_err("try to write RO reg %x\n", offset);
gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
gvt_vgpu_err("Unsupported registers %x\n", offset);
gvt_vgpu_err("eventfd_ctx_fdget failed\n");
gvt_vgpu_err("intel:vfio_set_irqs_validate_and_prepare failed\n");
gvt_vgpu_err("vfio_pin_pages failed for iova %pad, ret %d\n",
gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n",
gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n");
gvt_vgpu_err("invalid EDID blob\n");
gvt_vgpu_err("invalid EDID link state %d\n",
gvt_vgpu_err("EDID size is bigger than %d!\n",
gvt_vgpu_err("write read-only EDID region at offset %d\n",
gvt_vgpu_err("failed to access EDID region\n");
gvt_vgpu_err("KVM is required to use Intel vGPU\n");
gvt_vgpu_err("Invalid aperture offset %llu\n", off);
gvt_vgpu_err("invalid index: %u\n", index);
gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
gvt_vgpu_err("timeout in invalidate ring %s tlb\n",
gvt_vgpu_err("guest opregion read error %d, gpa 0x%llx, len %lu\n",
gvt_vgpu_err("guest opregion read error %d, gpa 0x%llx, len %lu\n",
gvt_vgpu_err("requesting SMI service\n");
gvt_vgpu_err("requesting runtime service: func \"%s\","
gvt_vgpu_err("guest opregion write error %d, gpa 0x%llx, len %lu\n",
gvt_vgpu_err("guest opregion write error %d, gpa 0x%llx, len %lu\n",
gvt_vgpu_err("fail to dispatch workload, skip\n");
gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start);
gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n",
gvt_vgpu_err("invalid per_ctx at: 0x%lx\n",
gvt_vgpu_err("Invalid guest context descriptor\n");
gvt_vgpu_err("invalid cmd found in guest context pages\n");
gvt_vgpu_err("fail to emit init breadcrumb\n");
gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n",
gvt_vgpu_err("fail to allocate gem request\n");
gvt_vgpu_err("fail to vgpu pin mm\n");
gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
gvt_vgpu_err("LRI shadow ppgtt fail to pin\n");
gvt_vgpu_err("fail to pin shadow mm\n");
gvt_vgpu_err("fail to vgpu sync oos pages\n");
gvt_vgpu_err("fail to flush post shadow\n");
gvt_vgpu_err("fail to generate request\n");
gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
gvt_vgpu_err("invalid guest context descriptor\n");