sys/dev/pci/drm/i915/gt/intel_engine_cs.c

319

gt_dbg(gt, "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

794

gt_dbg(gt, "vcs%u fused off\n", i);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

802

gt_dbg(gt, "vdbox enable: %04x, instances: %04lx\n", vdbox_mask, VDBOX_MASK(gt));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

813

gt_dbg(gt, "vecs%u fused off\n", i);

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

816

gt_dbg(gt, "vebox enable: %04x, instances: %04lx\n", vebox_mask, VEBOX_MASK(gt));

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

842

gt_dbg(gt, "ccs%u fused off\n", i);

sys/dev/pci/drm/i915/gt/intel_gt.c

1012

gt_dbg(gt, "Setting up %s\n", gt->name);

sys/dev/pci/drm/i915/gt/intel_gt.c

1035

gt_dbg(gt, "Setting up %s\n", gt->name);

sys/dev/pci/drm/i915/gt/intel_gt.c

265

gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir);

sys/dev/pci/drm/i915/gt/intel_gt.c

312

gt_dbg(gt, "Unexpected fault\n"

sys/dev/pci/drm/i915/gt/intel_gt.c

334

gt_dbg(gt, "Unexpected fault\n"

sys/dev/pci/drm/i915/gt/intel_gt.c

919

gt_dbg(gt, "Setting up %s\n", gt->name);

sys/dev/pci/drm/i915/gt/intel_gt.c

942

gt_dbg(gt, "Setting up %s\n", gt->name);

sys/dev/pci/drm/i915/gt/intel_gt_irq.c

401

gt_dbg(gt, "Command parser error, gt_iir 0x%08x\n", gt_iir);

sys/dev/pci/drm/i915/gt/intel_gt_print.h

40

gt_dbg(_gt, _fmt, ##__VA_ARGS__); \

sys/dev/pci/drm/i915/gt/intel_reset.c

1248

gt_dbg(gt, "GPU reset disabled\n");

sys/dev/pci/drm/i915/gt/intel_workarounds.c

126

gt_dbg(wal->gt, "Initialized %u %s workarounds on %s\n",

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

327

gt_dbg(gt, "GSC proxy mei component bound\n");

sys/dev/pci/drm/i915/gt/uc/intel_gsc_proxy.c

348

gt_dbg(gt, "GSC proxy mei component unbound\n");

sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc.c

85

gt_dbg(gt, "GSC Proxy initialized\n");

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

287

gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling HuC\n", ERR_PTR(err));

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

293

gt_dbg(gt, "Failed to fetch GuC fw (%pe) disabling GSC\n", ERR_PTR(err));

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

512

gt_dbg(gt, "GuC fw load failed (%pe) will reset and retry %d more time(s)\n",

sys/dev/pci/drm/i915/gt/uc/intel_uc.c

86

gt_dbg(gt, "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1268

gt_dbg(__uc_fw_to_gt(uc_fw), "%s fw pin-pages failed %pe\n",

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

1275

gt_dbg(__uc_fw_to_gt(uc_fw), "%s fw rsa data creation failed %pe\n",

sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c

57

gt_dbg(__uc_fw_to_gt(uc_fw), "%s firmware -> %s\n",

sys/dev/pci/drm/i915/gt/uc/selftest_guc_multi_lrc.c

122

gt_dbg(gt, "Not enough engines in class: %d\n", class);