for_each_intel_crtc_in_pipe_mask
for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) {
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {
for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) {
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) {
for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask)
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mst_pipe_mask) {
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {
for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {
for_each_intel_crtc_in_pipe_mask(display->drm, primary_crtc, primary_pipes_mask) {
for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, joiner_secondaries_mask)
for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, portsync_slaves_mask)
for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, portsync_master_mask)
for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc,
for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
for_each_intel_crtc_in_pipe_mask(state->base.dev, crtc, joined_pipes) {
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, dbuf_state->active_pipes)