regress/lib/libc/qsort/antiqsort.c

33

freeze(x);

regress/lib/libc/qsort/antiqsort.c

35

freeze(y);

sbin/iked/smult_curve25519_ref.c

262

freeze(work + 64);

sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c

3016

.freeze = pm_sleep_ptr(amdgpu_pmops_freeze),

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1560

u32 f32_cntl, freeze, cntl, stat1_reg;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1574

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1575

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1576

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1579

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1580

if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1611

u32 freeze;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1616

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1617

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c

1618

WREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1468

u32 f32_cntl, freeze, cntl, stat1_reg;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1482

freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1483

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1484

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1487

freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1489

if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1)

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1521

u32 freeze;

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1526

freeze = RREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1527

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);

sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c

1528

WREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);

sys/dev/pci/drm/amd/display/dmub/inc/dmub_cmd.h

5498

uint8_t freeze;

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

751

static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

753

return amdgpu_kv_notify_message_to_smu(adev, freeze ?

sys/dev/pci/drm/drm_mipi_dsi.c

91

.freeze = pm_generic_freeze,

sys/dev/pci/drm/i915/i915_driver.c

1712

.freeze = i915_pm_freeze,

sys/dev/pci/drm/radeon/kv_dpm.c

519

static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)

sys/dev/pci/drm/radeon/kv_dpm.c

521

return kv_notify_message_to_smu(rdev, freeze ?

sys/dev/pci/drm/radeon/radeon.h

2861

bool fbcon, bool freeze);

sys/dev/pci/drm/radeon/radeon_device.c

1577

bool notify_clients, bool freeze)

sys/dev/pci/drm/radeon/radeon_device.c

1669

if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {

sys/dev/pci/drm/radeon/radeon_drv.c

507

.freeze = radeon_pmops_freeze,

sys/dev/wscons/wstpad.c

1305

|| (tp->t->flags & tp->freeze)

sys/dev/wscons/wstpad.c

1653

tp->freeze = EDGES;

sys/dev/wscons/wstpad.c

180

u_int freeze;

usr.bin/ssh/smult_curve25519_ref.c

262

freeze(work + 64);