sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

400

force_update_wptr_for_self_int(adev, 0, 8, true);

sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c

417

force_update_wptr_for_self_int(adev, 0, 8, false);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

371

force_update_wptr_for_self_int(adev, 0, 8, true);

sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c

388

force_update_wptr_for_self_int(adev, 0, 8, false);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

371

force_update_wptr_for_self_int(adev, 0, 8, true);

sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c

388

force_update_wptr_for_self_int(adev, 0, 8, false);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

371

force_update_wptr_for_self_int(adev, 0, 8, true);

sys/dev/pci/drm/amd/amdgpu/navi10_ih.c

388

force_update_wptr_for_self_int(adev, 0, 8, false);