for_each_if
for_each_if(((plane) = __i->ptr, \
for_each_if ((__state)->private_objs[__i].ptr && \
for_each_if ((__state)->private_objs[__i].ptr && \
for_each_if(intel_phy_is_combo(__display, __phy))
for_each_if(intel_phy_is_combo(__display, __phy))
for_each_if((__lane_mask) & BIT(__lane))
for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
for_each_if((__mask) & BIT(__p))
for_each_if (DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
for_each_if ((__mask) & BIT(__t))
for_each_if((__ports_mask) & BIT(__port))
for_each_if((__phys_mask) & BIT(__phy))
for_each_if((plane_mask) & \
for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
for_each_if((pipe_mask) & BIT((intel_crtc)->pipe))
for_each_if((encoder_mask) & \
for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
for_each_if(intel_encoder_is_dp(intel_encoder))
for_each_if(intel_encoder_can_psr(intel_encoder))
for_each_if((intel_encoder)->base.crtc == (__crtc))
for_each_if(plane)
for_each_if(crtc)
for_each_if(plane)
for_each_if(crtc)
for_each_if(crtc)
for_each_if(plane)
for_each_if(crtc)
for_each_if(crtc)
for_each_if ((plane_state = \
for_each_if ((__state)->base.connectors[__i].ptr && \
for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
for_each_if((crtc) && ((first_pipes) | ((second_pipes) << I915_MAX_PIPES)) & BIT(i))
for_each_if((__crtc)->plane_ids_mask & BIT(__p))
for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
for_each_if((__mask) & BIT(__slice))
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
for_each_if(test_bit((__domain), (__mask)->bits))
for_each_if(DISPLAY_RUNTIME_INFO(__display)->fbc_mask & BIT(__fbc_id))
for_each_if((__fbc) = (__display)->fbc[(__fbc_id)])
for_each_if(obj)
for_each_if(obj)
for_each_if(obj)
for_each_if(((gt__) = (i915__)->gt[(id__)]))
for_each_if ((engine__) = (gt__)->engine[(id__)])
for_each_if(_HAS_SS(ss_, gt_, group_, instance_))
for_each_if(test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status))
for_each_if((mr) = (i915)->mm.regions[id])
for_each_if(domain__ = (uncore__)->fw_domain[__mask_next_bit(tmp__)])
for_each_if(__drm_dp_mst_state_iter_get((__state), &(mgr), &(old_state), &(new_state), (__i)))
for_each_if(__drm_dp_mst_state_iter_get((__state), &(mgr), &(old_state), NULL, (__i)))
for_each_if(__drm_dp_mst_state_iter_get((__state), &(mgr), NULL, &(new_state), (__i)))
for_each_if ((__state)->planes[__i].ptr && \
for_each_if ((__state)->planes[__i].ptr && \
for_each_if ((__state)->planes[__i].ptr && \
for_each_if ((__state)->planes[__i].ptr && \
for_each_if ((__state)->connectors[__i].ptr && \
for_each_if ((__state)->connectors[__i].ptr && \
for_each_if ((__state)->connectors[__i].ptr && \
for_each_if ((__state)->crtcs[__i].ptr && \
for_each_if ((__state)->crtcs[__i].ptr && \
for_each_if ((__state)->crtcs[__i].ptr && \
for_each_if ((__state)->planes[__i].ptr && \
for_each_if ((plane_state = \
for_each_if ((encoder_mask) & drm_encoder_mask(encoder))
for_each_if ((plane_mask) & drm_plane_mask(plane))
for_each_if (plane->type == DRM_PLANE_TYPE_OVERLAY)