fls
return ((unsigned)~0 >> (32 - fls(x)));
#define bmnum(_x) (fls(_x) - ffs(_x) + 1)
fb->depth = max(fb->depth, fls(bios_efiinfo->fb_red_mask));
fb->depth = max(fb->depth, fls(bios_efiinfo->fb_green_mask));
fb->depth = max(fb->depth, fls(bios_efiinfo->fb_blue_mask));
fb->depth = max(fb->depth, fls(bios_efiinfo->fb_reserved_mask));
fls(LPI_BASE + sc->sc_nlpi - 1) - 1);
size = 1 << fls(size);
size_t sz = 1 << (fls(size) - 1);
size_t sz = 1 << (fls(size) - 1);
bit = fls(ci->ci_ipending & mask) - 1;
nnodes = LS3_NODEID(fls(loongson_cpumask) - 1) + 1;
reg |= ((fls(div) - 1) << HHI_SYS_DPLL_OD_SHIFT);
cfg |= (fls(blklen) - 1) << SD_EMMC_CFG_BL_LEN_SHIFT;
shift = 8 - fls(mix->mask[ch]);
shift = 8 - fls(mix->mask[ch]);
i = fls(sc->hw_params.ring_mask->rx[grp_id]) - 1;
*n_link_desc = 1 << fls(*n_link_desc);
return (powerof2(i) ? i : (1 << (fls(i) - 1)));
i = fls(sc->hw_params.ring_mask->tx[grp_id]) - 1;
i = fls(sc->hw_params.ring_mask->rx[grp_id]) - 1;
*n_link_desc = 1 << fls(*n_link_desc);
return (powerof2(i) ? i : (1 << (fls(i) - 1)));
fls(adev->pm.pcie_mlw_mask)) - 1;
fls(adev->pm.pcie_gen_mask &
rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
dev_info->pcie_gen = fls(pcie_gen_mask);
last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
index = fls(hwmgr->workload_mask);
index = fls(hwmgr->workload_mask);
index = fls(hwmgr->workload_mask);
high = mask ? (fls(mask) - 1) : 0;
if (fls(tmp) != ffs(tmp))
fls(tmp) - 1,
data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
order = fls(pages) - 1;
order = min(order, (unsigned int)fls(pages) - 1);
order = fls(pages) - 1;
return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0;
for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
return fls(live_status_mask) - 1;
ddb->end = fls(slice_mask) * slice_size;
p = fls(pll_ctl);
int order = min(fls(npages) - 1, max_order);
n = fls(sz >> PAGE_SHIFT) - 1;
for (s = 0; s < fls(sseu->slice_mask); s++)
for (s = 0; s < fls(sseu->slice_mask); s++)
for (s = 0; s < fls(sseu->slice_mask); s++) {
u_long shift = fls(recip) - 1; \
#define ilog2(x) ((sizeof(x) <= 4) ? (fls(x) - 1) : (flsl(x) - 1))
sc->bge_expmrq = (fls(2048) - 8) << 12;
sc->bge_expmrq = (fls(4096) - 8) << 12;
sc->sc_nqueues = fls(nqueues) - 1;
#define ice_ilog2(x) ((sizeof(x) <= 4) ? (fls(x) - 1) : (flsl(x) - 1))
qid = fls(sc->qenablemsk);
#define IWX_RX_QUEUE_CB_SIZE(x) ((sizeof(x) <= 4) ? (fls(x) - 1) : (flsl(x) - 1))
sc->sc_nqueues = fls(nqueues) - 1;
pcireg_t dc = ((fls(4096) - 8) << 12) | PCI_PCIE_DCSR_ERO;
RGE_WRITE_2(sc, RGE_RXQUEUE_CTRL, val | (fls(sc->sc_nqueues) - 1) << 2);
((fls(sc->sc_nqueues) - 1) & 0x03) << 10);
fls(sc->sc_xr_size) - 1))
sc->sc_xr_size = 1 << (fls(sc->sc_xr_size) - 1);
sc->sc_xr_ndesc = 1 << (fls(sc->sc_xr_ndesc) - 1);
return (fls(ival) - 1);
nintrs = 1 << (fls(nintrs) - 1);
int fls(int);