sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

150

REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

641

CHUNK_SIZE, reg_vals->pps.slice_chunk_size);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

143

DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

318

type CHUNK_SIZE; \

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

103

REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

262

CHUNK_SIZE, reg_vals->pps.slice_chunk_size);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

81

DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1101

CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

586

CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

350

HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

551

type CHUNK_SIZE;\

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1332

CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1381

CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

210

CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

82

CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

153

CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

275

CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

451

CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

148

HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

132

HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

234

CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

840

CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

123

HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\