emuxki_write
emuxki_write(sc, chano, EMU_A_CHAN_FXRT1,
emuxki_write(sc, chano, EMU_A_CHAN_FXRT2,
emuxki_write(sc, chano, EMU_A_CHAN_SENDAMOUNTS,
emuxki_write(sc, chano, EMU_CHAN_FXRT,
emuxki_write(sc, chano, 0x10000000 | EMU_CHAN_PTRX,
emuxki_write(sc, chano, EMU_CHAN_DSL,
emuxki_write(sc, chano, EMU_CHAN_PSST,
emuxki_write(sc, chano, EMU_CHAN_CPF_STEREO, voice->stereo);
emuxki_write(sc, chano, EMU_CHAN_CCCA,
emuxki_write(sc, chano, EMU_CHAN_Z1, 0);
emuxki_write(sc, chano, EMU_CHAN_Z2, 0);
emuxki_write(sc, chano, EMU_CHAN_MAPA, mapval);
emuxki_write(sc, chano, EMU_CHAN_MAPB, mapval);
emuxki_write(sc, chano, EMU_CHAN_CVCF_CURRFILTER,
emuxki_write(sc, chano, EMU_CHAN_VTFT_FILTERTARGET,
emuxki_write(sc, chano, EMU_CHAN_ATKHLDM,
emuxki_write(sc, chano, EMU_CHAN_DCYSUSM,
emuxki_write(sc, chano, EMU_CHAN_LFOVAL1,
emuxki_write(sc, chano, EMU_CHAN_LFOVAL2,
emuxki_write(sc, chano, EMU_CHAN_FMMOD,
emuxki_write(sc, chano, EMU_CHAN_TREMFRQ,
emuxki_write(sc, chano, EMU_CHAN_FM2FRQ2,
emuxki_write(sc, chano, EMU_CHAN_ENVVAL,
emuxki_write(sc, chano, EMU_CHAN_ATKHLDV,
emuxki_write(sc, chano, EMU_CHAN_ENVVOL,
emuxki_write(sc, chano, EMU_CHAN_PEFE,
emuxki_write(sc, chano, EMU_CHAN_CD0 + cache_sample,
emuxki_write(sc, chano, EMU_CHAN_CCR_CACHEINVALIDSIZE, 0);
emuxki_write(sc, chano, EMU_CHAN_CCR_READADDRESS, 64);
emuxki_write(sc, chano, EMU_CHAN_CCR_CACHEINVALIDSIZE,
emuxki_write(sc, chano, EMU_CHAN_IFATN,
emuxki_write(sc, chano, EMU_CHAN_VTFT_VOLUMETARGET,
emuxki_write(sc, chano, EMU_CHAN_CVCF_CURRVOL,
emuxki_write(sc, 0,
emuxki_write(sc, 0,
emuxki_write(sc, chano, EMU_CHAN_DCYSUSV,
emuxki_write(sc, chano, EMU_CHAN_PTRX_PITCHTARGET,
emuxki_write(sc, chano, EMU_CHAN_CPF_PITCH,
emuxki_write(sc, chano, EMU_CHAN_IP, chan->pitch.initial);
emuxki_write(sc, chano, EMU_CHAN_PTRX_PITCHTARGET, 0);
emuxki_write(sc, chano, EMU_CHAN_CPF_PITCH, 0);
emuxki_write(sc, chano, EMU_CHAN_IFATN_ATTENUATION, 0xff);
emuxki_write(sc, chano, EMU_CHAN_VTFT_VOLUMETARGET, 0);
emuxki_write(sc, chano, EMU_CHAN_CVCF_CURRVOL, 0);
emuxki_write(sc, chano, EMU_CHAN_IP, 0);
emuxki_write(voice->sc, 0,
emuxki_write(voice->sc, 0,
emuxki_write(voice->sc, 0, EMU_ADCCR, 0);
emuxki_write(voice->sc, 0, EMU_ADCCR, val);
emuxki_write(voice->sc, 0, EMU_ADCCR, 0);
emuxki_write(voice->sc, 0,
emuxki_write(sc, 0,
emuxki_write(sc, 0, EMU_DSP_GPR(pc), 0);
emuxki_write(sc, 0, EMU_TANKMEMDATAREGBASE + pc, 0);
emuxki_write(sc, 0, EMU_TANKMEMADDRREGBASE + pc, 0);
emuxki_write(sc, 0, EMU_A_DBG, 0); /* Is it really necessary ? */
emuxki_write(sc, 0, EMU_DBG, 0); /* Is it really necessary ? */
emuxki_write(sc, 0, EMU_CLIEL, 0);
emuxki_write(sc, 0, EMU_CLIEH, 0);
emuxki_write(sc, 0, EMU_SOLEL, 0);
emuxki_write(sc, 0, EMU_SOLEH, 0);
emuxki_write(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
emuxki_write(sc, 0, EMU_MICBA, 0);
emuxki_write(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
emuxki_write(sc, 0, EMU_FXBA, 0);
emuxki_write(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
emuxki_write(sc, 0, EMU_ADCBA, 0);
emuxki_write(sc, 0, EMU_SPBYPASS, EMU_SPBYPASS_24_BITS);
emuxki_write(sc, 0, EMU_AC97SLOT, EMU_AC97SLOT_CENTER | EMU_AC97SLOT_LFE);
emuxki_write(sc, i, EMU_CHAN_DCYSUSV, 0);
emuxki_write(sc, i, EMU_CHAN_IP, 0);
emuxki_write(sc, i, EMU_CHAN_VTFT, 0xffff);
emuxki_write(sc, i, EMU_CHAN_CVCF, 0xffff);
emuxki_write(sc, i, EMU_CHAN_PTRX, 0);
emuxki_write(sc, i, EMU_CHAN_CPF, 0);
emuxki_write(sc, i, EMU_CHAN_CCR, 0);
emuxki_write(sc, i, EMU_CHAN_PSST, 0);
emuxki_write(sc, i, EMU_CHAN_DSL, 0x10); /* Why 16 ? */
emuxki_write(sc, i, EMU_CHAN_CCCA, 0);
emuxki_write(sc, i, EMU_CHAN_Z1, 0);
emuxki_write(sc, i, EMU_CHAN_Z2, 0);
emuxki_write(sc, i, EMU_CHAN_FXRT, 0x32100000);
emuxki_write(sc, i, EMU_CHAN_ATKHLDM, 0);
emuxki_write(sc, i, EMU_CHAN_DCYSUSM, 0);
emuxki_write(sc, i, EMU_CHAN_IFATN, 0xffff);
emuxki_write(sc, i, EMU_CHAN_PEFE, 0);
emuxki_write(sc, i, EMU_CHAN_FMMOD, 0);
emuxki_write(sc, i, EMU_CHAN_TREMFRQ, 24);
emuxki_write(sc, i, EMU_CHAN_FM2FRQ2, 24);
emuxki_write(sc, i, EMU_CHAN_TEMPENV, 0);
emuxki_write(sc, i, EMU_CHAN_LFOVAL2, 0);
emuxki_write(sc, i, EMU_CHAN_LFOVAL1, 0);
emuxki_write(sc, i, EMU_CHAN_ATKHLDV, 0);
emuxki_write(sc, i, EMU_CHAN_ENVVOL, 0);
emuxki_write(sc, i, EMU_CHAN_ENVVAL, 0);
emuxki_write(sc, 0, EMU_SPCS0, spcs);
emuxki_write(sc, 0, EMU_SPCS1, spcs);
emuxki_write(sc, 0, EMU_SPCS2, spcs);
emuxki_write(sc, 0, EMU_A_SPDIF_SAMPLERATE, tmp | 0x400);
emuxki_write(sc, 0, EMU_A2_SPDIF_SAMPLERATE, EMU_A2_SPDIF_UNKNOWN);
emuxki_write(sc, 0, EMU_PTB, DMAADDR(sc->ptb));
emuxki_write(sc, 0, EMU_TCBS, 0); /* This means 16K TCB */
emuxki_write(sc, 0, EMU_TCB, 0); /* No TCB use for now */
emuxki_write(sc, i, EMU_CHAN_MAPA, silentpage);
emuxki_write(sc, i, EMU_CHAN_MAPB, silentpage);
emuxki_write(sc, 0, EMU_CLIEL, 0);
emuxki_write(sc, 0, EMU_CLIEH, 0);
emuxki_write(sc, 0, EMU_SOLEL, 0);
emuxki_write(sc, 0, EMU_SOLEH, 0);
emuxki_write(sc, i, EMU_CHAN_DCYSUSV, 0);
emuxki_write(sc, i, EMU_CHAN_VTFT, 0);
emuxki_write(sc, i, EMU_CHAN_CVCF, 0);
emuxki_write(sc, i, EMU_CHAN_PTRX, 0);
emuxki_write(sc, i, EMU_CHAN_CPF, 0);
emuxki_write(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
emuxki_write(sc, 0, EMU_MICBA, 0);
emuxki_write(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
emuxki_write(sc, 0, EMU_FXBA, 0);
emuxki_write(sc, 0, EMU_A_FXWC1, 0);
emuxki_write(sc, 0, EMU_A_FXWC2, 0);
emuxki_write(sc, 0, EMU_FXWC, 0);
emuxki_write(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
emuxki_write(sc, 0, EMU_ADCBA, 0);
emuxki_write(sc, 0, EMU_TCB, 0); /* 16K again */
emuxki_write(sc, 0, EMU_TCBS, 0);
emuxki_write(sc, 0, EMU_DBG, 0x8000); /* necessary ? */