Symbol: dwqe_write
sys/dev/ic/dwqe.c
1001
dwqe_write(sc, GMAC_MTL_CHAN_TX_OP_MODE(0), mode);
sys/dev/ic/dwqe.c
1006
dwqe_write(sc, GMAC_QX_TX_FLOW_CTRL(0), reg);
sys/dev/ic/dwqe.c
1009
dwqe_write(sc, GMAC_RX_FLOW_CTRL, reg);
sys/dev/ic/dwqe.c
1011
dwqe_write(sc, GMAC_RXQ_CTRL0, GMAC_RXQ_CTRL0_DCB_QUEUE_EN(0));
sys/dev/ic/dwqe.c
1013
dwqe_write(sc, GMAC_MAC_CONF, dwqe_read(sc, GMAC_MAC_CONF) |
sys/dev/ic/dwqe.c
1017
dwqe_write(sc, GMAC_CHAN_INTR_ENA(0),
sys/dev/ic/dwqe.c
1030
dwqe_write(sc, GMAC_MAC_CONF, reg);
sys/dev/ic/dwqe.c
1053
dwqe_write(sc, GMAC_MAC_CONF, reg);
sys/dev/ic/dwqe.c
1058
dwqe_write(sc, GMAC_CHAN_RX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
1063
dwqe_write(sc, GMAC_CHAN_TX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
1068
dwqe_write(sc, GMAC_MTL_CHAN_TX_OP_MODE(0), reg);
sys/dev/ic/dwqe.c
1084
dwqe_write(sc, GMAC_MAC_CONF, reg);
sys/dev/ic/dwqe.c
1086
dwqe_write(sc, GMAC_CHAN_INTR_ENA(0), 0);
sys/dev/ic/dwqe.c
1170
dwqe_write(sc, GMAC_MAC_HASH_TAB_REG0, hash[0]);
sys/dev/ic/dwqe.c
1171
dwqe_write(sc, GMAC_MAC_HASH_TAB_REG1, hash[1]);
sys/dev/ic/dwqe.c
1173
dwqe_write(sc, GMAC_MAC_PACKET_FILTER, reg);
sys/dev/ic/dwqe.c
122
dwqe_write(sc, GMAC_VLAN_TAG_CTRL, reg);
sys/dev/ic/dwqe.c
1304
dwqe_write(sc, GMAC_BUS_MODE, dwqe_read(sc, GMAC_BUS_MODE) |
sys/dev/ic/dwqe.c
1421
dwqe_write(sc, GMAC_CHAN_RX_END_ADDR(0), DWQE_DMA_DVA(sc->sc_rxring) +
sys/dev/ic/dwqe.c
146
dwqe_write(sc, GMAC_VLAN_TAG_INCL, reg);
sys/dev/ic/dwqe.c
217
dwqe_write(sc, GMAC_SYS_BUS_MODE, mode);
sys/dev/ic/dwqe.c
223
dwqe_write(sc, GMAC_CHAN_CONTROL(0), mode);
sys/dev/ic/dwqe.c
229
dwqe_write(sc, GMAC_CHAN_TX_CONTROL(0), mode);
sys/dev/ic/dwqe.c
233
dwqe_write(sc, GMAC_CHAN_RX_CONTROL(0), mode);
sys/dev/ic/dwqe.c
279
dwqe_write(sc, GMAC_SYS_BUS_MODE, mode);
sys/dev/ic/dwqe.c
297
dwqe_write(sc, GMAC_INT_EN, 0);
sys/dev/ic/dwqe.c
298
dwqe_write(sc, GMAC_CHAN_INTR_ENA(0), 0);
sys/dev/ic/dwqe.c
299
dwqe_write(sc, GMAC_MMC_RX_INT_MASK, 0xffffffff);
sys/dev/ic/dwqe.c
300
dwqe_write(sc, GMAC_MMC_TX_INT_MASK, 0xffffffff);
sys/dev/ic/dwqe.c
372
dwqe_write(sc, GMAC_MAC_ADDR0_HI,
sys/dev/ic/dwqe.c
374
dwqe_write(sc, GMAC_MAC_ADDR0_LO,
sys/dev/ic/dwqe.c
433
dwqe_write(sc, GMAC_CHAN_TX_END_ADDR(0), DWQE_DMA_DVA(sc->sc_txring) +
sys/dev/ic/dwqe.c
526
dwqe_write(sc, GMAC_MAC_MDIO_ADDR,
sys/dev/ic/dwqe.c
549
dwqe_write(sc, GMAC_MAC_MDIO_DATA, val);
sys/dev/ic/dwqe.c
550
dwqe_write(sc, GMAC_MAC_MDIO_ADDR,
sys/dev/ic/dwqe.c
60
void dwqe_write(struct dwqe_softc *, bus_addr_t, uint32_t);
sys/dev/ic/dwqe.c
600
dwqe_write(sc, GMAC_MAC_CONF, conf);
sys/dev/ic/dwqe.c
631
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR_HI(0), 0);
sys/dev/ic/dwqe.c
632
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR(0), 0);
sys/dev/ic/dwqe.c
641
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR_HI(0), DWQE_DMA_DVA(sc->sc_rxring) >> 32);
sys/dev/ic/dwqe.c
642
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR(0), DWQE_DMA_DVA(sc->sc_rxring));
sys/dev/ic/dwqe.c
656
dwqe_write(sc, GMAC_INT_STATUS, reg);
sys/dev/ic/dwqe.c
659
dwqe_write(sc, GMAC_CHAN_STATUS(0), reg);
sys/dev/ic/dwqe.c
899
dwqe_write(sc, GMAC_CHAN_TX_BASE_ADDR_HI(0), DWQE_DMA_DVA(sc->sc_txring) >> 32);
sys/dev/ic/dwqe.c
900
dwqe_write(sc, GMAC_CHAN_TX_BASE_ADDR(0), DWQE_DMA_DVA(sc->sc_txring));
sys/dev/ic/dwqe.c
901
dwqe_write(sc, GMAC_CHAN_TX_RING_LEN(0), DWQE_NTXDESC - 1);
sys/dev/ic/dwqe.c
902
dwqe_write(sc, GMAC_CHAN_TX_END_ADDR(0), DWQE_DMA_DVA(sc->sc_txring));
sys/dev/ic/dwqe.c
921
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR_HI(0), DWQE_DMA_DVA(sc->sc_rxring) >> 32);
sys/dev/ic/dwqe.c
922
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR(0), DWQE_DMA_DVA(sc->sc_rxring));
sys/dev/ic/dwqe.c
923
dwqe_write(sc, GMAC_CHAN_RX_RING_LEN(0), DWQE_NRXDESC - 1);
sys/dev/ic/dwqe.c
944
dwqe_write(sc, GMAC_MAC_1US_TIC_CTR, (sc->sc_clkrate / 1000000) - 1);
sys/dev/ic/dwqe.c
949
dwqe_write(sc, GMAC_CHAN_RX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
954
dwqe_write(sc, GMAC_CHAN_TX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
980
dwqe_write(sc, GMAC_MTL_CHAN_RX_OP_MODE(0), mode);
sys/dev/ic/dwqevar.h
120
void dwqe_write(struct dwqe_softc *, bus_addr_t, uint32_t);