Symbol: dwqe_write
sys/dev/ic/dwqe.c
1003
dwqe_write(sc, GMAC_CHAN_INTR_ENA(0),
sys/dev/ic/dwqe.c
1016
dwqe_write(sc, GMAC_MAC_CONF, reg);
sys/dev/ic/dwqe.c
1039
dwqe_write(sc, GMAC_MAC_CONF, reg);
sys/dev/ic/dwqe.c
1044
dwqe_write(sc, GMAC_CHAN_RX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
1049
dwqe_write(sc, GMAC_CHAN_TX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
1054
dwqe_write(sc, GMAC_MTL_CHAN_TX_OP_MODE(0), reg);
sys/dev/ic/dwqe.c
1070
dwqe_write(sc, GMAC_MAC_CONF, reg);
sys/dev/ic/dwqe.c
1072
dwqe_write(sc, GMAC_CHAN_INTR_ENA(0), 0);
sys/dev/ic/dwqe.c
1156
dwqe_write(sc, GMAC_MAC_HASH_TAB_REG0, hash[0]);
sys/dev/ic/dwqe.c
1157
dwqe_write(sc, GMAC_MAC_HASH_TAB_REG1, hash[1]);
sys/dev/ic/dwqe.c
1159
dwqe_write(sc, GMAC_MAC_PACKET_FILTER, reg);
sys/dev/ic/dwqe.c
122
dwqe_write(sc, GMAC_VLAN_TAG_CTRL, reg);
sys/dev/ic/dwqe.c
1291
dwqe_write(sc, GMAC_BUS_MODE, dwqe_read(sc, GMAC_BUS_MODE) |
sys/dev/ic/dwqe.c
1407
dwqe_write(sc, GMAC_CHAN_RX_END_ADDR(0), DWQE_DMA_DVA(sc->sc_rxring) +
sys/dev/ic/dwqe.c
146
dwqe_write(sc, GMAC_VLAN_TAG_INCL, reg);
sys/dev/ic/dwqe.c
203
dwqe_write(sc, GMAC_SYS_BUS_MODE, mode);
sys/dev/ic/dwqe.c
209
dwqe_write(sc, GMAC_CHAN_CONTROL(0), mode);
sys/dev/ic/dwqe.c
215
dwqe_write(sc, GMAC_CHAN_TX_CONTROL(0), mode);
sys/dev/ic/dwqe.c
219
dwqe_write(sc, GMAC_CHAN_RX_CONTROL(0), mode);
sys/dev/ic/dwqe.c
265
dwqe_write(sc, GMAC_SYS_BUS_MODE, mode);
sys/dev/ic/dwqe.c
283
dwqe_write(sc, GMAC_INT_EN, 0);
sys/dev/ic/dwqe.c
284
dwqe_write(sc, GMAC_CHAN_INTR_ENA(0), 0);
sys/dev/ic/dwqe.c
285
dwqe_write(sc, GMAC_MMC_RX_INT_MASK, 0xffffffff);
sys/dev/ic/dwqe.c
286
dwqe_write(sc, GMAC_MMC_TX_INT_MASK, 0xffffffff);
sys/dev/ic/dwqe.c
358
dwqe_write(sc, GMAC_MAC_ADDR0_HI,
sys/dev/ic/dwqe.c
360
dwqe_write(sc, GMAC_MAC_ADDR0_LO,
sys/dev/ic/dwqe.c
419
dwqe_write(sc, GMAC_CHAN_TX_END_ADDR(0), DWQE_DMA_DVA(sc->sc_txring) +
sys/dev/ic/dwqe.c
512
dwqe_write(sc, GMAC_MAC_MDIO_ADDR,
sys/dev/ic/dwqe.c
535
dwqe_write(sc, GMAC_MAC_MDIO_DATA, val);
sys/dev/ic/dwqe.c
536
dwqe_write(sc, GMAC_MAC_MDIO_ADDR,
sys/dev/ic/dwqe.c
586
dwqe_write(sc, GMAC_MAC_CONF, conf);
sys/dev/ic/dwqe.c
60
void dwqe_write(struct dwqe_softc *, bus_addr_t, uint32_t);
sys/dev/ic/dwqe.c
617
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR_HI(0), 0);
sys/dev/ic/dwqe.c
618
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR(0), 0);
sys/dev/ic/dwqe.c
627
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR_HI(0), DWQE_DMA_DVA(sc->sc_rxring) >> 32);
sys/dev/ic/dwqe.c
628
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR(0), DWQE_DMA_DVA(sc->sc_rxring));
sys/dev/ic/dwqe.c
642
dwqe_write(sc, GMAC_INT_STATUS, reg);
sys/dev/ic/dwqe.c
645
dwqe_write(sc, GMAC_CHAN_STATUS(0), reg);
sys/dev/ic/dwqe.c
885
dwqe_write(sc, GMAC_CHAN_TX_BASE_ADDR_HI(0), DWQE_DMA_DVA(sc->sc_txring) >> 32);
sys/dev/ic/dwqe.c
886
dwqe_write(sc, GMAC_CHAN_TX_BASE_ADDR(0), DWQE_DMA_DVA(sc->sc_txring));
sys/dev/ic/dwqe.c
887
dwqe_write(sc, GMAC_CHAN_TX_RING_LEN(0), DWQE_NTXDESC - 1);
sys/dev/ic/dwqe.c
888
dwqe_write(sc, GMAC_CHAN_TX_END_ADDR(0), DWQE_DMA_DVA(sc->sc_txring));
sys/dev/ic/dwqe.c
907
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR_HI(0), DWQE_DMA_DVA(sc->sc_rxring) >> 32);
sys/dev/ic/dwqe.c
908
dwqe_write(sc, GMAC_CHAN_RX_BASE_ADDR(0), DWQE_DMA_DVA(sc->sc_rxring));
sys/dev/ic/dwqe.c
909
dwqe_write(sc, GMAC_CHAN_RX_RING_LEN(0), DWQE_NRXDESC - 1);
sys/dev/ic/dwqe.c
930
dwqe_write(sc, GMAC_MAC_1US_TIC_CTR, (sc->sc_clkrate / 1000000) - 1);
sys/dev/ic/dwqe.c
935
dwqe_write(sc, GMAC_CHAN_RX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
940
dwqe_write(sc, GMAC_CHAN_TX_CONTROL(0), reg);
sys/dev/ic/dwqe.c
966
dwqe_write(sc, GMAC_MTL_CHAN_RX_OP_MODE(0), mode);
sys/dev/ic/dwqe.c
987
dwqe_write(sc, GMAC_MTL_CHAN_TX_OP_MODE(0), mode);
sys/dev/ic/dwqe.c
992
dwqe_write(sc, GMAC_QX_TX_FLOW_CTRL(0), reg);
sys/dev/ic/dwqe.c
995
dwqe_write(sc, GMAC_RX_FLOW_CTRL, reg);
sys/dev/ic/dwqe.c
997
dwqe_write(sc, GMAC_RXQ_CTRL0, GMAC_RXQ_CTRL0_DCB_QUEUE_EN(0));
sys/dev/ic/dwqe.c
999
dwqe_write(sc, GMAC_MAC_CONF, dwqe_read(sc, GMAC_MAC_CONF) |
sys/dev/ic/dwqevar.h
119
void dwqe_write(struct dwqe_softc *, bus_addr_t, uint32_t);