sys/dev/fdt/if_dwqe_fdt.c

240

sc->sc_hw_feature[i] = dwqe_read(sc, GMAC_MAC_HW_FEATURE(i));

sys/dev/ic/dwqe.c

1014

reg = dwqe_read(sc, GMAC_MAC_CONF);

sys/dev/ic/dwqe.c

1037

reg = dwqe_read(sc, GMAC_MAC_CONF);

sys/dev/ic/dwqe.c

1042

reg = dwqe_read(sc, GMAC_CHAN_RX_CONTROL(0));

sys/dev/ic/dwqe.c

1047

reg = dwqe_read(sc, GMAC_CHAN_TX_CONTROL(0));

sys/dev/ic/dwqe.c

1052

reg = dwqe_read(sc, GMAC_MTL_CHAN_TX_OP_MODE(0));

sys/dev/ic/dwqe.c

1057

reg = dwqe_read(sc, GMAC_MTL_CHAN_TX_OP_MODE(0));

sys/dev/ic/dwqe.c

1068

reg = dwqe_read(sc, GMAC_MAC_CONF);

sys/dev/ic/dwqe.c

120

reg = dwqe_read(sc, GMAC_VLAN_TAG_CTRL);

sys/dev/ic/dwqe.c

1291

dwqe_write(sc, GMAC_BUS_MODE, dwqe_read(sc, GMAC_BUS_MODE) |

sys/dev/ic/dwqe.c

1295

if ((dwqe_read(sc, GMAC_BUS_MODE) &

sys/dev/ic/dwqe.c

132

reg = dwqe_read(sc, GMAC_VLAN_TAG_INCL);

sys/dev/ic/dwqe.c

157

version = dwqe_read(sc, GMAC_VERSION);

sys/dev/ic/dwqe.c

162

sc->sc_hw_feature[i] = dwqe_read(sc, GMAC_MAC_HW_FEATURE(i));

sys/dev/ic/dwqe.c

196

mode = dwqe_read(sc, GMAC_SYS_BUS_MODE);

sys/dev/ic/dwqe.c

206

mode = dwqe_read(sc, GMAC_CHAN_CONTROL(0));

sys/dev/ic/dwqe.c

211

mode = dwqe_read(sc, GMAC_CHAN_TX_CONTROL(0));

sys/dev/ic/dwqe.c

216

mode = dwqe_read(sc, GMAC_CHAN_RX_CONTROL(0));

sys/dev/ic/dwqe.c

225

mode = dwqe_read(sc, GMAC_SYS_BUS_MODE);

sys/dev/ic/dwqe.c

340

machi = dwqe_read(sc, GMAC_MAC_ADDR0_HI);

sys/dev/ic/dwqe.c

341

maclo = dwqe_read(sc, GMAC_MAC_ADDR0_LO);

sys/dev/ic/dwqe.c

521

if ((dwqe_read(sc, GMAC_MAC_MDIO_ADDR) & GMAC_MAC_MDIO_ADDR_GB) == 0)

sys/dev/ic/dwqe.c

522

return dwqe_read(sc, GMAC_MAC_MDIO_DATA);

sys/dev/ic/dwqe.c

545

if ((dwqe_read(sc, GMAC_MAC_MDIO_ADDR) & GMAC_MAC_MDIO_ADDR_GB) == 0)

sys/dev/ic/dwqe.c

559

conf = dwqe_read(sc, GMAC_MAC_CONF);

sys/dev/ic/dwqe.c

59

uint32_t dwqe_read(struct dwqe_softc *, bus_addr_t);

sys/dev/ic/dwqe.c

641

reg = dwqe_read(sc, GMAC_INT_STATUS);

sys/dev/ic/dwqe.c

644

reg = dwqe_read(sc, GMAC_CHAN_STATUS(0));

sys/dev/ic/dwqe.c

933

reg = dwqe_read(sc, GMAC_CHAN_RX_CONTROL(0));

sys/dev/ic/dwqe.c

938

reg = dwqe_read(sc, GMAC_CHAN_TX_CONTROL(0));

sys/dev/ic/dwqe.c

942

mode = dwqe_read(sc, GMAC_MTL_CHAN_RX_OP_MODE(0));

sys/dev/ic/dwqe.c

968

mode = dwqe_read(sc, GMAC_MTL_CHAN_TX_OP_MODE(0));

sys/dev/ic/dwqe.c

989

reg = dwqe_read(sc, GMAC_QX_TX_FLOW_CTRL(0));

sys/dev/ic/dwqe.c

993

reg = dwqe_read(sc, GMAC_RX_FLOW_CTRL);

sys/dev/ic/dwqe.c

999

dwqe_write(sc, GMAC_MAC_CONF, dwqe_read(sc, GMAC_MAC_CONF) |

sys/dev/ic/dwqevar.h

118

uint32_t dwqe_read(struct dwqe_softc *, bus_addr_t);