sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1047

const struct dsc_enc_caps *dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1055

struct dsc_enc_caps dsc_common_caps;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1081

is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps, timing->pixel_encoding, &dsc_common_caps);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1303

struct dsc_enc_caps dsc_enc_caps;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1305

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1307

min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1310

&dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

157

const struct dsc_enc_caps *dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

164

const struct dsc_enc_caps *dsc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

178

struct dsc_enc_caps *dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

183

const struct dsc_enc_caps *dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

185

struct dsc_enc_caps *dsc_common_caps);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

189

const struct dsc_enc_caps *dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

470

struct dsc_enc_caps dsc_enc_caps;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

471

struct dsc_enc_caps dsc_common_caps;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

479

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

481

min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

483

is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, &dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

487

is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

500

struct dsc_enc_caps dsc_enc_caps;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

502

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

505

DC_LOG_DSC("\tdsc_version 0x%x", dsc_enc_caps.dsc_version);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

506

DC_LOG_DSC("\tslice_caps 0x%x", dsc_enc_caps.slice_caps.raw);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

507

DC_LOG_DSC("\tlb_bit_depth %d", dsc_enc_caps.lb_bit_depth);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

508

DC_LOG_DSC("\tis_block_pred_supported %d", dsc_enc_caps.is_block_pred_supported);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

509

DC_LOG_DSC("\tcolor_formats 0x%x", dsc_enc_caps.color_formats.raw);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

510

DC_LOG_DSC("\tcolor_depth 0x%x", dsc_enc_caps.color_depth.raw);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

511

DC_LOG_DSC("\tmax_total_throughput_mps %d", dsc_enc_caps.max_total_throughput_mps);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

512

DC_LOG_DSC("\tmax_slice_width %d", dsc_enc_caps.max_slice_width);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

513

DC_LOG_DSC("\tbpp_increment_div %d", dsc_enc_caps.bpp_increment_div);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

541

const struct dsc_enc_caps *single_dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

542

struct dsc_enc_caps *dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

546

dsc_enc_caps->slice_caps.raw |= single_dsc_enc_caps->slice_caps.raw;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

551

dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

554

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

557

dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

560

dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_8;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

566

dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

572

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

575

dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

578

dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_3;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

581

dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

587

struct dsc_enc_caps *dsc_enc_caps)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

592

struct dsc_enc_caps single_dsc_enc_caps;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

610

dsc_enc_caps->dsc_version = single_dsc_enc_caps.dsc_version;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

611

dsc_enc_caps->lb_bit_depth = single_dsc_enc_caps.lb_bit_depth;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

612

dsc_enc_caps->is_block_pred_supported = single_dsc_enc_caps.is_block_pred_supported;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

613

dsc_enc_caps->max_slice_width = single_dsc_enc_caps.max_slice_width;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

614

dsc_enc_caps->bpp_increment_div = single_dsc_enc_caps.bpp_increment_div;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

615

dsc_enc_caps->color_formats.raw = single_dsc_enc_caps.color_formats.raw;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

616

dsc_enc_caps->color_depth.raw = single_dsc_enc_caps.color_depth.raw;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

622

dsc_enc_caps->max_total_throughput_mps =

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

627

build_dsc_enc_combined_slice_caps(&single_dsc_enc_caps, dsc_enc_caps, max_odm_combine_factor);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

637

const struct dsc_enc_caps *dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

643

max_dispclk_khz = dsc_enc_caps->max_total_throughput_mps * 1000;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

653

if (max_dispclk_khz == 0 || dsc_enc_caps->max_slice_width == 0)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

664

dsc_enc_caps->max_slice_width))); // slice width

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

669

struct dsc_enc_caps *dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

672

memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

679

dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

681

build_dsc_enc_caps(dsc, dsc_enc_caps);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

685

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

693

const struct dsc_enc_caps *dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

695

struct dsc_enc_caps *dsc_common_caps)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

700

memset(dsc_common_caps, 0, sizeof(struct dsc_enc_caps));

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

702

dsc_common_caps->dsc_version = min(dsc_sink_caps->dsc_version, dsc_enc_caps->dsc_version);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

707

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_1 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

709

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_2 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

711

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_4 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

713

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_8 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_8;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

715

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_12 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_12;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

717

dsc_sink_caps->slice_caps2.bits.NUM_SLICES_16 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_16;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

722

dsc_common_caps->lb_bit_depth = min(dsc_sink_caps->lb_bit_depth, dsc_enc_caps->lb_bit_depth);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

727

dsc_sink_caps->is_block_pred_supported && dsc_enc_caps->is_block_pred_supported;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

729

dsc_common_caps->color_formats.raw = dsc_sink_caps->color_formats.raw & dsc_enc_caps->color_formats.raw;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

733

dsc_common_caps->color_depth.raw = dsc_sink_caps->color_depth.raw & dsc_enc_caps->color_depth.raw;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

751

dsc_common_caps->max_total_throughput_mps = min(total_sink_throughput, dsc_enc_caps->max_total_throughput_mps);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

753

dsc_common_caps->max_slice_width = min(dsc_sink_caps->max_slice_width, dsc_enc_caps->max_slice_width);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

757

dsc_common_caps->bpp_increment_div = min(dsc_sink_caps->bpp_increment_div, dsc_enc_caps->bpp_increment_div);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

801

const struct dsc_enc_caps *dsc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

856

const struct dsc_enc_caps *dsc_common_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

100

dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

101

dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

102

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

103

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

105

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

106

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

107

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

114

dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

120

dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

121

dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

122

dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

129

dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

130

dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

131

dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 4;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

134

dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

135

dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

87

void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

89

dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

91

dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

92

dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

93

dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

94

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

96

dsc_enc_caps->lb_bit_depth = 13;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

97

dsc_enc_caps->is_block_pred_supported = true;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

99

dsc_enc_caps->color_formats.bits.RGB = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

601

void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

17

static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

65

static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz)

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

67

dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

69

dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

70

dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

71

dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

72

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

74

dsc_enc_caps->lb_bit_depth = 13;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

75

dsc_enc_caps->is_block_pred_supported = true;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

77

dsc_enc_caps->color_formats.bits.RGB = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

78

dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

79

dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

80

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

81

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

83

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

84

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

85

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

86

dsc_enc_caps->max_total_throughput_mps = max_dscclk_khz * 3 / 1000;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

88

dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

89

dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

100

void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

111

void (*dsc_get_single_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);