dwhdmi_write
dwhdmi_write(sc, HDMI_I2CM_SOFTRSTZ, 0);
dwhdmi_write(sc, HDMI_IH_I2CM_STAT0, dwhdmi_read(sc, HDMI_IH_I2CM_STAT0));
dwhdmi_write(sc, HDMI_I2CM_SS_SCL_HCNT_0_ADDR, sc->sc_scl_hcnt);
dwhdmi_write(sc, HDMI_I2CM_SS_SCL_LCNT_0_ADDR, sc->sc_scl_lcnt);
dwhdmi_write(sc, HDMI_I2CM_DIV, 0);
dwhdmi_write(sc, HDMI_I2CM_SLAVE, DDC_ADDR);
dwhdmi_write(sc, HDMI_I2CM_SEGADDR, DDC_SEGMENT_ADDR);
dwhdmi_write(sc, HDMI_I2CM_SEGPTR, block >> 1);
dwhdmi_write(sc, HDMI_I2CM_ADDRESS, n + off);
dwhdmi_write(sc, HDMI_I2CM_OPERATION, operation);
dwhdmi_write(sc, HDMI_IH_I2CM_STAT0, val);
dwhdmi_write(sc, HDMI_VP_PR_CD, val);
dwhdmi_write(sc, HDMI_VP_STUFF, val);
dwhdmi_write(sc, HDMI_VP_REMAP, val);
dwhdmi_write(sc, HDMI_VP_CONF, val);
dwhdmi_write(sc, HDMI_TX_INVID0, val);
dwhdmi_write(sc, HDMI_TX_INSTUFFING, val);
dwhdmi_write(sc, HDMI_FC_INVIDCONF, val);
dwhdmi_write(sc, HDMI_FC_INHACTIV0, inhactiv & 0xff);
dwhdmi_write(sc, HDMI_FC_INHACTIV1, inhactiv >> 8);
dwhdmi_write(sc, HDMI_FC_INHBLANK0, inhblank & 0xff);
dwhdmi_write(sc, HDMI_FC_INHBLANK1, inhblank >> 8);
dwhdmi_write(sc, HDMI_FC_INVACTIV0, invactiv & 0xff);
dwhdmi_write(sc, HDMI_FC_INVACTIV1, invactiv >> 8);
dwhdmi_write(sc, HDMI_FC_INVBLANK, invblank);
dwhdmi_write(sc, HDMI_FC_HSYNCINDELAY0, hsyncindelay & 0xff);
dwhdmi_write(sc, HDMI_FC_HSYNCINDELAY1, hsyncindelay >> 8);
dwhdmi_write(sc, HDMI_FC_HSYNCINWIDTH0, hsyncinwidth & 0xff);
dwhdmi_write(sc, HDMI_FC_HSYNCINWIDTH1, hsyncinwidth >> 8);
dwhdmi_write(sc, HDMI_FC_VSYNCINDELAY, vsyncindelay);
dwhdmi_write(sc, HDMI_FC_VSYNCINWIDTH, vsyncinwidth);
dwhdmi_write(sc, HDMI_FC_CTRLDUR, HDMI_FC_CTRLDUR_DEFAULT);
dwhdmi_write(sc, HDMI_FC_EXCTRLDUR, HDMI_FC_EXCTRLDUR_DEFAULT);
dwhdmi_write(sc, HDMI_FC_EXCTRLSPAC, HDMI_FC_EXCTRLSPAC_DEFAULT);
dwhdmi_write(sc, HDMI_FC_CH0PREAM, HDMI_FC_CH0PREAM_DEFAULT);
dwhdmi_write(sc, HDMI_FC_CH1PREAM, HDMI_FC_CH1PREAM_DEFAULT);
dwhdmi_write(sc, HDMI_FC_CH2PREAM, HDMI_FC_CH2PREAM_DEFAULT);
dwhdmi_write(sc, HDMI_MC_FLOWCTRL, 0);
dwhdmi_write(sc, HDMI_MC_CLKDIS, val);
dwhdmi_write(sc, HDMI_MC_SWRSTZREQ, val);
dwhdmi_write(sc, HDMI_FC_INVIDCONF, val);
dwhdmi_write(sc, HDMI_MC_CLKDIS, 0xff);
dwhdmi_write(sc, HDMI_AUD_CTS1, 0);
dwhdmi_write(sc, HDMI_AUD_CTS2, 0);
dwhdmi_write(sc, HDMI_AUD_CTS3, 0);
dwhdmi_write(sc, HDMI_AUD_N1, n & 0xff);
dwhdmi_write(sc, HDMI_AUD_N2, (n >> 8) & 0xff);
dwhdmi_write(sc, HDMI_AUD_N3, (n >> 16) & 0xff);
dwhdmi_write(sc, HDMI_AUD_CONF0, val);
dwhdmi_write(sc, HDMI_AUD_CONF1, val);
dwhdmi_write(sc, HDMI_AUD_INPUTCLKFS, 4); /* XXX 64 FS */
dwhdmi_write(sc, HDMI_FC_AUDCONF0, 1 << 4); /* XXX 2ch */
dwhdmi_write(sc, HDMI_FC_AUDCONF1, 0);
dwhdmi_write(sc, HDMI_FC_AUDCONF2, 0);
dwhdmi_write(sc, HDMI_FC_AUDCONF3, 0);
dwhdmi_write(sc, HDMI_MC_CLKDIS, val);
dwhdmi_write(sc, HDMI_PHY_CONF0, val);
void dwhdmi_write(struct dwhdmi_softc *, bus_size_t, uint8_t);
dwhdmi_write(sc, HDMI_IH_I2CMPHY_STAT0,
dwhdmi_write(sc, HDMI_PHY_I2CM_ADDRESS_ADDR, addr);
dwhdmi_write(sc, HDMI_PHY_I2CM_DATAO_1_ADDR, ((data >> 8) & 0xff));
dwhdmi_write(sc, HDMI_PHY_I2CM_DATAO_0_ADDR, ((data >> 0) & 0xff));
dwhdmi_write(sc, HDMI_PHY_I2CM_OPERATION_ADDR, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE);
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
dwhdmi_write(sc, HDMI_PHY_CONF0, reg);
dwhdmi_write(sc, HDMI_PHY_TST0, val);
dwhdmi_write(sc, HDMI_MC_FLOWCTRL, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS);
dwhdmi_write(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_DEASSERT);
dwhdmi_write(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_ASSERT);
dwhdmi_write(sc, HDMI_MC_HEACPHY_RST, HDMI_MC_HEACPHY_RST_ASSERT);
dwhdmi_write(sc, HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);