dwhdmi_read
dwhdmi_write(sc, HDMI_IH_I2CM_STAT0, dwhdmi_read(sc, HDMI_IH_I2CM_STAT0));
val = dwhdmi_read(sc, HDMI_IH_I2CM_STAT0);
printf("dwhdmi_ddc_exec: timeout waiting for xfer, stat0=%#x\n", dwhdmi_read(sc, HDMI_IH_I2CM_STAT0));
pbuf[n] = dwhdmi_read(sc, HDMI_I2CM_DATAI);
val = dwhdmi_read(sc, HDMI_FC_INVIDCONF);
val = dwhdmi_read(sc, HDMI_AUD_CONF0);
val = dwhdmi_read(sc, HDMI_MC_CLKDIS);
sc->sc_version = dwhdmi_read(sc, HDMI_DESIGN_ID);
sc->sc_version |= dwhdmi_read(sc, HDMI_REVISION_ID);
sc->sc_phytype = dwhdmi_read(sc, HDMI_CONFIG2_ID);
val = dwhdmi_read(sc, HDMI_PHY_CONF0);
uint8_t dwhdmi_read(struct dwhdmi_softc *, bus_size_t);
val = dwhdmi_read(sc, HDMI_IH_I2CMPHY_STAT0) &
val = dwhdmi_read(sc, HDMI_IH_I2CMPHY_STAT0) &
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
reg = dwhdmi_read(sc, HDMI_PHY_CONF0);
val = dwhdmi_read(sc, HDMI_PHY_TST0);
val = dwhdmi_read(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
val = dwhdmi_read(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
val = dwhdmi_read(sc, HDMI_PHY_STAT0);