dwge_write
dwge_write(sc, GMAC_TX_DESC_LIST_ADDR, DWGE_DMA_DVA(sc->sc_txring));
dwge_write(sc, GMAC_RX_DESC_LIST_ADDR, DWGE_DMA_DVA(sc->sc_rxring));
dwge_write(sc, GMAC_INT_ENA, GMAC_INT_ENA_NIE |
dwge_write(sc, GMAC_OP_MODE, mode | GMAC_OP_MODE_ST | GMAC_OP_MODE_SR);
dwge_write(sc, GMAC_MAC_CONF, dwge_read(sc, GMAC_MAC_CONF) |
dwge_write(sc, GMAC_MAC_CONF, dwge_read(sc,
dwge_write(sc, GMAC_OP_MODE, dmactrl);
dwge_write(sc, GMAC_INT_ENA, 0);
dwge_write(sc, GMAC_HASH_TAB_HI, hash[1]);
dwge_write(sc, GMAC_HASH_TAB_LO, hash[0]);
dwge_write(sc, GMAC_MAC_FRM_FILT, reg);
dwge_write(sc, GMAC_BUS_MODE, dwge_read(sc, GMAC_BUS_MODE) |
dwge_write(sc, GMAC_OP_MODE, dmactrl);
dwge_write(sc, GMAC_MAC_MMC_CTRL, GMAC_MAC_MMC_CTRL_ROR |
void dwge_write(struct dwge_softc *, bus_addr_t, uint32_t);
dwge_write(sc, GMAC_MAC_CONF, dwge_read(sc, GMAC_MAC_CONF) |
dwge_write(sc, GMAC_BUS_MODE, mode);
dwge_write(sc, GMAC_AXI_BUS_MODE, mode);
dwge_write(sc, GMAC_INT_ENA, 0);
dwge_write(sc, GMAC_INT_MASK,
dwge_write(sc, GMAC_MMC_IPC_INT_MSK, 0xffffffff);
dwge_write(sc, GMAC_MAC_ADDR0_HI,
dwge_write(sc, GMAC_MAC_ADDR0_LO,
dwge_write(sc, GMAC_TX_POLL_DEMAND, 0xffffffff);
dwge_write(sc, GMAC_GMII_ADDR,
dwge_write(sc, GMAC_GMII_DATA, val);
dwge_write(sc, GMAC_GMII_ADDR,
dwge_write(sc, GMAC_MAC_CONF, conf);
dwge_write(sc, GMAC_OP_MODE, mode & ~GMAC_OP_MODE_SR);
dwge_write(sc, GMAC_RX_DESC_LIST_ADDR, 0);
dwge_write(sc, GMAC_RX_DESC_LIST_ADDR, DWGE_DMA_DVA(sc->sc_rxring));
dwge_write(sc, GMAC_OP_MODE, mode);
dwge_write(sc, GMAC_STATUS, reg);