Symbol: dwbc
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
481
struct dwbc *dwb;
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
502
dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
523
struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
535
struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
553
struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
633
struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
45
static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
64
static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
66
struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
69
dwbc->funcs->disable(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
81
static bool dwb1_disable(struct dwbc *dwbc)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.c
83
struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dwb.h
254
struct dwbc base;
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
101
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
121
dwb2_config_dwb_cnv(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
124
dwb2_set_scaler(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
135
bool dwb2_disable(struct dwbc *dwbc)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
137
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
158
static bool dwb2_update(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
160
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
185
dwb2_config_dwb_cnv(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
188
dwb2_set_scaler(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
198
bool dwb2_is_enabled(struct dwbc *dwbc)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
200
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
210
void dwb2_set_stereo(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
213
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
226
void dwb2_set_new_content(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
229
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
235
static void dwb2_set_warmup(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
238
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
250
void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
252
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
50
static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
52
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
72
void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
74
struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.c
99
static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
389
struct dwbc base;
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
402
bool dwb2_disable(struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
404
bool dwb2_is_enabled(struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
406
void dwb2_set_stereo(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
409
void dwb2_set_new_content(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
412
void dwb2_config_dwb_cnv(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_dwb.h
415
void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
100
dwb3_config_fc(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
103
dwb3_program_hdr_mult(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
104
dwb3_set_gamut_remap(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
105
dwb3_ogam_set_input_transfer_func(dwbc, params->out_transfer_func);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
108
dwb3_set_denorm(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
119
bool dwb3_disable(struct dwbc *dwbc)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
121
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
129
DC_LOG_DWB("%s dwb3_disabled at inst = %d", __func__, dwbc->inst);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
133
void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
135
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
151
DC_LOG_DWB("%s dwb3_fc_disabled at inst = %d", __func__, dwbc->inst);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
155
bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
157
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
167
DC_LOG_DWB("%s dwb update, inst = %d", __func__, dwbc->inst);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
175
dwb3_config_fc(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
178
dwb3_program_hdr_mult(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
179
dwb3_set_gamut_remap(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
180
dwb3_ogam_set_input_transfer_func(dwbc, params->out_transfer_func);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
183
dwb3_set_denorm(dwbc, params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
193
bool dwb3_is_enabled(struct dwbc *dwbc)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
195
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
205
void dwb3_set_stereo(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
208
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
220
void dwb3_set_new_content(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
223
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
228
void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
230
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
46
static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
66
void dwb3_config_fc(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
68
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
88
dwb3_set_stereo(dwbc, &params->stereo_params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
91
bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
93
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c
94
DC_LOG_DWB("%s dwb3_enabled at inst = %d", __func__, dwbc->inst);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
871
struct dwbc base;
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
884
bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
886
bool dwb3_disable(struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
888
bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
890
bool dwb3_is_enabled(struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
892
void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
894
void dwb3_set_stereo(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
897
void dwb3_set_new_content(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
900
void dwb3_config_fc(struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
903
void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
906
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
910
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h
914
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
273
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
276
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
286
cm_helper_translate_curve_to_hw_format(dwbc->ctx,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
301
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
306
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
356
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
359
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
365
dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS);
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
379
dwb3_program_gamut_remap(dwbc, arr_reg_val,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
382
dwb3_program_gamut_remap(dwbc, arr_reg_val,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
389
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c
392
struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2542
struct dwbc *dwb;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2548
dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2568
struct dwbc *dwb;
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
2572
dwb = dc->res_pool->dwbc[dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3223
res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
331
res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
455
struct dwbc *dwb;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
456
dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
472
struct dwbc *dwb;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
478
dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
529
struct dwbc *dwb;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
532
dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
555
struct dwbc *dwb;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
559
dwb = dc->res_pool->dwbc[dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
578
struct dwbc *dwb;
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
623
dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
260
struct dwbc *dwbc[MAX_DWB_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
494
struct dwbc *dwbc;
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
177
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
181
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
184
bool (*disable)(struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
187
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
191
struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
194
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
198
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
202
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
206
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
211
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
215
struct dwbc *dwbc, unsigned int *buf_idx,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
220
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
225
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
230
struct dwbc *dwbc,
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
234
struct dwbc *dwbc, uint32_t *time_stamp);
sys/dev/pci/drm/amd/display/dc/inc/hw/dwb.h
237
struct dwbc *dwbc);
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1149
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1150
kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1151
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2255
pool->dwbc[i] = &dwbc20->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
719
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
720
kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
721
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1140
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1141
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1142
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1235
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1111
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1112
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1113
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
1195
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1063
if (pool->dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1064
kfree(TO_DCN30_DWBC(pool->dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
1065
pool->dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
723
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1007
if (pool->dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1008
kfree(TO_DCN30_DWBC(pool->dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
1009
pool->dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
684
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1441
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1442
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1443
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
1533
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1499
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1500
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1501
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
1591
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1441
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1442
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1443
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
1533
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1437
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1438
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1439
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
1526
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1447
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1448
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1449
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
1528
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1427
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1428
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1429
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1508
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1510
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1511
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1512
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
1622
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1490
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1491
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1492
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
1602
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1491
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1492
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1493
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
1603
pool->dwbc[i] = &dwbc30->base;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1450
if (pool->base.dwbc[i] != NULL) {
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1451
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1452
pool->base.dwbc[i] = NULL;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1532
pool->dwbc[i] = &dwbc401->base;