Symbol: dscceComputeDelay
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1808
dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1822
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4259
dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4272
2.0 * (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
48
static unsigned int dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1844
dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1858
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4380
dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4393
2.0 * (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
49
static unsigned int dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1800
dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1814
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4474
dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4487
2.0 * (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
73
static unsigned int dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2073
v->DSCDelay[k] = dscceComputeDelay(v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2081
v->DSCDelay[k] = 2 * dscceComputeDelay(v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2089
v->DSCDelay[k] = 4 * dscceComputeDelay(v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4140
v->DSCDelayPerState[i][k] = dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4149
* dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4158
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
72
static unsigned int dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2256
v->DSCDelay[k] = dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2265
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2274
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4594
v->DSCDelayPerState[i][k] = dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4603
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4612
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
93
static unsigned int dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
102
static unsigned int dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2274
v->DSCDelay[k] = dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2283
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2292
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4682
v->DSCDelayPerState[i][k] = dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4691
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4700
* (dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
175
static dml_uint_t dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5887
DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)(dml_ceil((dml_float_t) HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5890
DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)(dml_ceil((dml_float_t) HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5893
DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)((dml_float_t) dml_ceil(HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4510
DSCDelayRequirement_val = NumberOfDSCSlicesFactor * (dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (unsigned int)(math_ceil2((double)HActive / (double)NumberOfDSCSlices, 1.0)),