sys/arch/luna88k/cbus/if_ne_cbus.c

113

struct dp8390_softc *dsc = &nsc->sc_dp8390;

sys/arch/luna88k/cbus/if_ne_cbus.c

149

dsc->sc_regt = nict;

sys/arch/luna88k/cbus/if_ne_cbus.c

150

dsc->sc_regh = nich;

sys/arch/luna88k/cbus/if_ne_cbus.c

171

struct dp8390_softc *dsc = &nsc->sc_dp8390;

sys/arch/luna88k/cbus/if_ne_cbus.c

181

printf("%s: can't map i/o space\n", dsc->sc_dev.dv_xname);

sys/arch/luna88k/cbus/if_ne_cbus.c

187

printf("%s: can't subregion i/o space\n", dsc->sc_dev.dv_xname);

sys/arch/luna88k/cbus/if_ne_cbus.c

191

dsc->sc_regt = nict;

sys/arch/luna88k/cbus/if_ne_cbus.c

192

dsc->sc_regh = nich;

sys/arch/luna88k/cbus/if_ne_cbus.c

217

dsc->sc_mediachange = rtl80x9_mediachange;

sys/arch/luna88k/cbus/if_ne_cbus.c

218

dsc->sc_mediastatus = rtl80x9_mediastatus;

sys/arch/luna88k/cbus/if_ne_cbus.c

219

dsc->init_card = rtl80x9_init_card;

sys/arch/luna88k/cbus/if_ne_cbus.c

220

dsc->sc_media_init = rtl80x9_media_init;

sys/arch/luna88k/cbus/if_ne_cbus.c

232

dsc->sc_enabled = 1;

sys/arch/luna88k/cbus/if_ne_cbus.c

241

if (cbus_isrlink(dp8390_intr, dsc, caa->ca_int, IPL_NET,

sys/arch/luna88k/cbus/if_ne_cbus.c

242

dsc->sc_dev.dv_xname) != 0)

sys/dev/fdt/rkdwhdmi.c

261

rkdwhdmi_enable(struct dwhdmi_softc *dsc)

sys/dev/fdt/rkdwhdmi.c

263

dwhdmi_phy_enable(dsc);

sys/dev/fdt/rkdwhdmi.c

267

rkdwhdmi_mode_set(struct dwhdmi_softc *dsc,

sys/dev/fdt/rkdwhdmi.c

270

struct rkdwhdmi_softc *sc = to_rkdwhdmi_softc(dsc);

sys/dev/fdt/rkdwhdmi.c

278

dsc->sc_dev.dv_xname, adjusted_mode->clock * 1000,

sys/dev/fdt/rkdwhdmi.c

282

dwhdmi_phy_mode_set(dsc, mode, adjusted_mode);

sys/dev/fdt/rkdwhdmi.c

286

rkdwhdmi_mode_valid(struct dwhdmi_softc *dsc, const struct drm_display_mode *mode)

sys/dev/fdt/rkdwhdmi.c

288

struct rkdwhdmi_softc *sc = to_rkdwhdmi_softc(dsc);

sys/dev/ic/ne2000.c

134

dsc->cr_proto = ED_CR_RD2;

sys/dev/ic/ne2000.c

137

dsc->rcr_proto = ED_RCR_INTT;

sys/dev/ic/ne2000.c

138

dsc->sc_flags |= DP8390_DO_AX88190_WORKAROUND;

sys/dev/ic/ne2000.c

140

dsc->rcr_proto = 0;

sys/dev/ic/ne2000.c

150

dsc->dcr_reg = ED_DCR_FT1 | ED_DCR_LS | (useword ? ED_DCR_WTS : 0);

sys/dev/ic/ne2000.c

152

dsc->test_mem = ne2000_test_mem;

sys/dev/ic/ne2000.c

153

dsc->ring_copy = ne2000_ring_copy;

sys/dev/ic/ne2000.c

154

dsc->write_mbuf = ne2000_write_mbuf;

sys/dev/ic/ne2000.c

155

dsc->read_hdr = ne2000_read_hdr;

sys/dev/ic/ne2000.c

159

dsc->sc_reg_map[i] = i;

sys/dev/ic/ne2000.c

166

dsc->mem_start = memsize;

sys/dev/ic/ne2000.c

231

dsc->mem_start = mstart;

sys/dev/ic/ne2000.c

235

dsc->mem_size = memsize;

sys/dev/ic/ne2000.c

250

AX88190_NODEID_OFFSET, dsc->sc_arpcom.ac_enaddr,

sys/dev/ic/ne2000.c

256

dsc->sc_arpcom.ac_enaddr[i] =

sys/dev/ic/ne2000.c

260

bcopy(myea, dsc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);

sys/dev/ic/ne2000.c

267

if (dsc->sc_media_init == NULL)

sys/dev/ic/ne2000.c

268

dsc->sc_media_init = dp8390_media_init;

sys/dev/ic/ne2000.c

270

if (dp8390_config(dsc)) {

sys/dev/ic/ne2000.c

284

struct dp8390_softc *dsc = &nsc->sc_dp8390;

sys/dev/ic/ne2000.c

285

bus_space_tag_t nict = dsc->sc_regt;

sys/dev/ic/ne2000.c

286

bus_space_handle_t nich = dsc->sc_regh;

sys/dev/ic/ne2000.c

293

state = dsc->sc_enabled;

sys/dev/ic/ne2000.c

294

dsc->sc_enabled = 0;

sys/dev/ic/ne2000.c

441

dsc->sc_enabled = state;

sys/dev/ic/ne2000.c

95

struct dp8390_softc *dsc = &nsc->sc_dp8390;

sys/dev/ic/ne2000.c

96

bus_space_tag_t nict = dsc->sc_regt;

sys/dev/ic/ne2000.c

97

bus_space_handle_t nich = dsc->sc_regh;

sys/dev/ic/rtl80x9.c

60

rtl80x9_mediachange(struct dp8390_softc *dsc)

sys/dev/ic/rtl80x9.c

68

dp8390_reset(dsc);

sys/dev/isa/if_ne_isa.c

114

dsc->sc_regt = nict;

sys/dev/isa/if_ne_isa.c

115

dsc->sc_regh = nich;

sys/dev/isa/if_ne_isa.c

136

struct dp8390_softc *dsc = &nsc->sc_dp8390;

sys/dev/isa/if_ne_isa.c

146

printf("%s: can't map i/o space\n", dsc->sc_dev.dv_xname);

sys/dev/isa/if_ne_isa.c

152

printf("%s: can't subregion i/o space\n", dsc->sc_dev.dv_xname);

sys/dev/isa/if_ne_isa.c

156

dsc->sc_regt = nict;

sys/dev/isa/if_ne_isa.c

157

dsc->sc_regh = nich;

sys/dev/isa/if_ne_isa.c

179

dsc->sc_mediachange = rtl80x9_mediachange;

sys/dev/isa/if_ne_isa.c

180

dsc->sc_mediastatus = rtl80x9_mediastatus;

sys/dev/isa/if_ne_isa.c

181

dsc->init_card = rtl80x9_init_card;

sys/dev/isa/if_ne_isa.c

182

dsc->sc_media_init = rtl80x9_media_init;

sys/dev/isa/if_ne_isa.c

194

dsc->sc_enabled = 1;

sys/dev/isa/if_ne_isa.c

204

IPL_NET, dp8390_intr, dsc, dsc->sc_dev.dv_xname);

sys/dev/isa/if_ne_isa.c

88

struct dp8390_softc *dsc = &nsc->sc_dp8390;

sys/dev/isa/if_ne_isapnp.c

112

printf("%s: can't subregion i/o space\n", dsc->sc_dev.dv_xname);

sys/dev/isa/if_ne_isapnp.c

116

dsc->sc_regt = nict;

sys/dev/isa/if_ne_isapnp.c

117

dsc->sc_regh = nich;

sys/dev/isa/if_ne_isapnp.c

144

dsc->sc_mediachange = rtl80x9_mediachange;

sys/dev/isa/if_ne_isapnp.c

145

dsc->sc_mediastatus = rtl80x9_mediastatus;

sys/dev/isa/if_ne_isapnp.c

146

dsc->init_card = rtl80x9_init_card;

sys/dev/isa/if_ne_isapnp.c

147

dsc->sc_media_init = rtl80x9_media_init;

sys/dev/isa/if_ne_isapnp.c

159

dsc->sc_enabled = 1;

sys/dev/isa/if_ne_isapnp.c

169

IST_EDGE, IPL_NET, dp8390_intr, dsc,

sys/dev/isa/if_ne_isapnp.c

170

dsc->sc_dev.dv_xname);

sys/dev/isa/if_ne_isapnp.c

96

struct dp8390_softc * const dsc = &nsc->sc_dp8390;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7113

!aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1559

struct display_stream_compressor *dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1580

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1581

if (dsc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1582

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1745

struct display_stream_compressor *dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1766

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1767

if (dsc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1768

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1929

struct display_stream_compressor *dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1950

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1951

if (dsc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1952

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2109

struct display_stream_compressor *dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2130

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2131

if (dsc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2132

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2284

struct display_stream_compressor *dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2305

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2306

if (dsc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2307

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2338

struct display_stream_compressor *dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2359

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2360

if (dsc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2361

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2407

struct display_stream_compressor *dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2428

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2429

if (dsc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2430

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2476

struct display_stream_compressor *dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2497

dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2498

if (dsc)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2499

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1138

panel_config->dsc.disable_dsc_edp = false;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1139

panel_config->dsc.force_dsc_edp_policy = 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1148

panel_config->dsc.disable_dsc_edp = true;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

4912

if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5466

sec_pipe->stream_res.dsc = NULL;

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5474

dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, sec_pipe->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5476

ASSERT(sec_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5477

if (sec_pipe->stream_res.dsc == NULL)

sys/dev/pci/drm/amd/display/dc/dc.h

778

bool dsc: 1;

sys/dev/pci/drm/amd/display/dc/dc.h

806

bool dsc : 1; /* Display stream compression */

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

71

const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

81

const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

97

void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dc_dsc.h

99

void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dc_types.h

1233

} dsc;

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

358

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

402

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

141

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1859

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1867

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1875

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1883

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

399

!link->panel_config.dsc.disable_dsc_edp &&

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

183

!link->panel_config.dsc.disable_dsc_edp &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1893

sec_pipe->stream_res.dsc = NULL;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1917

dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1918

ASSERT(sec_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1919

if (sec_pipe->stream_res.dsc == NULL)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2005

if (pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2006

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

146

timing->dsc.enable = dml2_dsc_enable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

147

timing->dsc.overrides.num_slices = stream->timing.dsc_cfg.num_slices_h;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

148

timing->dsc.dsc_compressed_bpp_x16 = stream->timing.dsc_cfg.bits_per_pixel;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

150

timing->dsc.enable = dml2_dsc_disable;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

263

} dsc;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

161

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

177

} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

178

out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

183

DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8365

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable ||

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8366

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8368

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8369

mode_lib->ms.support.NumberOfDSCSlices[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8443

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8481

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8491

DML_LOG_VERBOSE("DML::%s: k=%d num_slices = %d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8658

if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 && !mode_lib->ip.dsc422_native_support)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

339

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

355

} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

356

out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

362

DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

124

if (pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_mall_phantom.c

125

ctx->config.svp_pstate.callbacks.release_dsc(&context->res_ctx, ctx->config.svp_pstate.callbacks.dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h

141

void (*release_dsc)(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1294

const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1305

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

1307

min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

156

const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

177

const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

37

dsc->ctx->logger

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

459

const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

479

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

481

min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

497

void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

502

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

516

void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

586

const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

596

if (!dsc || !dsc->ctx || !dsc->ctx->dc || !dsc->funcs->dsc_get_single_enc_caps)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

599

dc = dsc->ctx->dc;

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

607

dsc->funcs->dsc_get_single_enc_caps(&single_dsc_enc_caps, max_dscclk_khz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

636

const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

644

if (dsc && dsc->ctx->dc) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

645

if (dsc->ctx->dc->clk_mgr &&

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

646

dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

648

max_dispclk_khz = dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz(dsc->ctx->dc->clk_mgr, CLK_TYPE_DISPCLK);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

668

const struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

674

if (!dsc || !dsc->ctx || !dsc->ctx->dc || dsc->ctx->dc->debug.disable_dsc)

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

678

if (dsc->funcs->dsc_get_enc_caps) {

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

679

dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

681

build_dsc_enc_caps(dsc, dsc_enc_caps);

sys/dev/pci/drm/amd/display/dc/dsc/dc_dsc.c

684

if (dsc->ctx->dc->debug.native422_support)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

142

void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

144

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

159

bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

162

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

171

void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

182

void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

186

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

188

DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

189

dsc_config_log(dsc, dsc_cfg);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

193

dsc_log_pps(dsc, &dsc20->reg_vals.pps);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

194

dsc_write_to_registers(dsc, &dsc20->reg_vals);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

198

bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

208

dsc_config_log(dsc, dsc_cfg);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

213

dsc_log_pps(dsc, &dsc_reg_vals.pps);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

219

void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

221

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

226

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

231

DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

244

void dsc2_disable(struct display_stream_compressor *dsc)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

246

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

249

DC_LOG_DSC("disable DSC %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

253

DC_LOG_DSC("DSC %d already disabled!", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

263

void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

265

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

270

void dsc2_disconnect(struct display_stream_compressor *dsc)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

272

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

274

DC_LOG_DSC("disconnect DSC %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

281

void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

33

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

578

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

58

dsc->ctx->logger

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

581

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

62

void dsc2_construct(struct dcn20_dsc *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

69

dsc->base.ctx = ctx;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

70

dsc->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

71

dsc->base.funcs = &dcn20_dsc_funcs;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

73

dsc->dsc_regs = dsc_regs;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

74

dsc->dsc_shift = dsc_shift;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

75

dsc->dsc_mask = dsc_mask;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

77

dsc->max_image_width = 5184;

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

31

#define TO_DCN20_DSC(dsc)\

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

32

container_of(dsc, struct dcn20_dsc, base)

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

572

void dsc_config_log(struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

575

void dsc_log_pps(struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

594

void dsc2_construct(struct dcn20_dsc *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

604

bool dsc2_get_packed_pps(struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

608

void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

609

bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

610

void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

612

void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

613

void dsc2_disable(struct display_stream_compressor *dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

614

void dsc2_disconnect(struct display_stream_compressor *dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

615

void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

30

static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

57

dsc->ctx->logger

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

59

void dsc35_construct(struct dcn20_dsc *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

66

dsc->base.ctx = ctx;

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

67

dsc->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

68

dsc->base.funcs = &dcn35_dsc_funcs;

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

70

dsc->dsc_regs = dsc_regs;

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

71

dsc->dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift);

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

72

dsc->dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask);

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

74

dsc->max_image_width = 5184;

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

77

static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe)

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

79

struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

84

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

97

DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h

50

void dsc35_construct(struct dcn20_dsc *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

112

bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

115

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

12

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

123

void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

127

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

129

DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

130

dsc_config_log(dsc, dsc_cfg);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

134

dsc_log_pps(dsc, &dsc401->reg_vals.pps);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

135

dsc_write_to_registers(dsc, &dsc401->reg_vals);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

138

void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

140

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

145

DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

150

DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

163

void dsc401_disable(struct display_stream_compressor *dsc)

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

165

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

168

DC_LOG_DSC("disable DSC %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

172

DC_LOG_DSC("DSC %d already disabled!", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

182

void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

184

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

189

void dsc401_disconnect(struct display_stream_compressor *dsc)

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

191

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

193

DC_LOG_DSC("disconnect DSC %d", dsc->inst);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

199

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

202

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

42

dsc->ctx->logger

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

47

void dsc401_construct(struct dcn401_dsc *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

54

dsc->base.ctx = ctx;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

55

dsc->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

56

dsc->base.funcs = &dcn401_dsc_funcs;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

58

dsc->dsc_regs = dsc_regs;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

59

dsc->dsc_shift = dsc_shift;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

60

dsc->dsc_mask = dsc_mask;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

62

dsc->max_image_width = 5184;

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

95

void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

97

struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

13

#define TO_DCN401_DSC(dsc)\

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

14

container_of(dsc, struct dcn401_dsc, base)

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

328

void dsc401_construct(struct dcn401_dsc *dsc,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

337

void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

338

bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

339

void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

341

void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

342

void dsc401_disable(struct display_stream_compressor *dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

343

void dsc401_disconnect(struct display_stream_compressor *dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

344

void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

101

void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

102

bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

103

void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

105

bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

107

void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

108

void (*dsc_disable)(struct display_stream_compressor *dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

109

void (*dsc_disconnect)(struct display_stream_compressor *dsc);

sys/dev/pci/drm/amd/display/dc/dsc/dsc.h

110

void (*dsc_wait_disconnect_pending_clear)(struct display_stream_compressor *dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1858

struct display_stream_compressor *dsc = NULL;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1872

dsc = dc->res_pool->dscs[i];

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1873

dsc->funcs->dsc_read_state(dsc, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1891

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1892

dsc->funcs->dsc_disable(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1896

pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

686

struct display_stream_compressor *dsc = pool->dscs[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

689

dsc->funcs->dsc_read_state(dsc, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

691

dsc->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2214

struct display_stream_compressor *dsc = opp_head->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2223

if (dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2227

is_dsc_ungated = dc->hwseq->funcs.dsc_pg_status(dc->hwseq, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2236

dsc->funcs->dsc_wait_disconnect_pending_clear(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2237

dsc->funcs->dsc_disable(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2239

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2615

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2618

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2620

hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2630

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2633

hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2635

hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

293

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

336

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

112

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

113

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

115

struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

139

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

141

ASSERT(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

142

odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

209

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

216

current_pipe_ctx->next_odm_pipe->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

217

struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

219

dsc->funcs->dsc_disconnect(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

236

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

287

if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

74

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

79

ASSERT(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

89

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

94

if (dsc->funcs->dsc_read_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

95

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1015

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1033

ASSERT(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1043

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1048

if (dsc->funcs->dsc_read_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1049

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1068

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1069

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1070

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1072

struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1096

dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1098

ASSERT(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1099

odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1160

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1167

current_pipe_ctx->next_odm_pipe->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1168

struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1171

dsc->funcs->dsc_disconnect(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1521

struct display_stream_compressor *dsc = dc->res_pool->dscs[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1522

bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1526

hws->funcs.dsc_pg_control(hws, dsc->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1530

hws->funcs.dsc_pg_control(hws, dsc->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1056

if (j == PG_DSC && new_pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1057

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1088

cur_pipe->stream_res.dsc != new_pipe->stream_res.dsc &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1089

new_pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1090

update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1127

if (new_pipe->stream_res.dsc && !new_pipe->top_pipe &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1128

update_state->pg_pipe_res_update[PG_DSC][new_pipe->stream_res.dsc->inst]) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1129

update_state->pg_pipe_res_update[PG_HUBP][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1130

update_state->pg_pipe_res_update[PG_DPP][new_pipe->stream_res.dsc->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1134

new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

329

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

336

ASSERT(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

346

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

351

if (dsc->funcs->dsc_read_state) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

352

dsc->funcs->dsc_read_state(dsc, &dsc_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

368

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

369

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

371

struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

395

dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

397

ASSERT(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

398

odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

465

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

472

current_pipe_ctx->next_odm_pipe->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

473

struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

475

dsc->funcs->dsc_disconnect(dsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

964

if (pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

965

update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

967

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

968

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

972

pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1548

if (otg_master->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1551

if (old_otg_master && old_otg_master->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1555

if (old_pipe->stream_res.dsc && !new_pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1556

old_pipe->stream_res.dsc->funcs->dsc_disconnect(

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1557

old_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

348

struct display_stream_compressor *dsc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1012

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1017

if (!dsc)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1036

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

1040

if (!dsc)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

750

static void dsc_optc_config_log(struct display_stream_compressor *dsc,

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

757

DC_LOGGER_INIT(dsc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

807

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

824

DC_LOGGER_INIT(dsc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

846

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

847

dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

848

dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

850

struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

865

dsc_optc_config_log(dsc, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

877

dsc_optc_config_log(dsc, &dsc_optc_cfg);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

908

odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

930

odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

932

dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

948

struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

954

if (!dsc)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

957

DC_LOGGER_INIT(dsc->ctx->logger);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

974

dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

369

|| link->panel_config.dsc.disable_dsc_edp

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

823

policy = link->panel_config.dsc.force_dsc_edp_policy;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

975

if (link->panel_config.dsc.force_dsc_edp_policy) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1063

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1066

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1071

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1072

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1075

void dcn20_dsc_destroy(struct display_stream_compressor **dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1077

kfree(container_of(*dsc, struct dcn20_dsc, base));

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1078

*dsc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1327

struct display_stream_compressor **dsc,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1332

struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1334

ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1335

*dsc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1339

*dsc = pool->dscs[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1346

*dsc = dsc_old;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1354

*dsc = pool->dscs[i];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1362

struct display_stream_compressor **dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1367

if (pool->dscs[i] == *dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1369

*dsc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1393

if (pipe_ctx->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1396

dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1399

if (!pipe_ctx->stream_res.dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1421

if (pipe_ctx->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1422

dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1496

next_odm_pipe->stream_res.dsc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1524

dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1525

ASSERT(next_odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1526

if (next_odm_pipe->stream_res.dsc == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1552

secondary_pipe->stream_res.dsc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1672

if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1780

if (odm_pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1781

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2214

if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2215

dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

103

void dcn20_dsc_destroy(struct display_stream_compressor **dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

134

struct display_stream_compressor **dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

148

struct display_stream_compressor **dsc,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1092

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1095

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1100

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1101

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1268

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1271

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1276

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1277

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1539

sec_pipe->stream_res.dsc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1562

dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1563

ASSERT(sec_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1564

if (sec_pipe->stream_res.dsc == NULL)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1741

if (pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1742

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1228

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1231

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1236

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1237

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

682

struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

684

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

689

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

690

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

643

struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

645

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

650

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

651

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1566

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1569

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1574

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1575

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1624

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1627

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1632

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1633

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

914

.dsc = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1566

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1569

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1574

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1575

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1559

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1562

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1567

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1568

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1565

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1568

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1580

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1582

dsc->max_image_width = 6016;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1584

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2851

free_pipe->stream_res.dsc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2863

&free_pipe->stream_res.dsc,

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2865

ASSERT(free_pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2866

if (free_pipe->stream_res.dsc == NULL) {

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

131

if (pipe->stream_res.dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

132

dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1545

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1548

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1560

dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1562

dsc->max_image_width = 6016;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1564

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1671

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1674

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1686

dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1687

dsc35_set_fgcg(dsc,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1688

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1689

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

753

.dsc = true,/*dscclk and dsc pg*/

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1651

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1654

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1666

dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1667

dsc35_set_fgcg(dsc,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1668

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1669

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

733

.dsc = true,/*dscclk and dsc pg*/

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1652

struct dcn20_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1655

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1667

dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1668

dsc35_set_fgcg(dsc,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1669

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1670

return &dsc->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

734

.dsc = true,/*dscclk and dsc pg*/

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1347

static void dcn401_dsc_destroy(struct display_stream_compressor **dsc)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1349

kfree(container_of(*dsc, struct dcn401_dsc, base));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1350

*dsc = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1570

struct dcn401_dsc *dsc =

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1573

if (!dsc) {

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1585

dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1586

dsc401_set_fgcg(dsc,

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1587

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1590

dsc->max_image_width = 5760;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1592

return &dsc->base;

sys/dev/pci/drm/amd/display/modules/power/power_helpers.c

953

link->panel_config.dsc.disable_dsc_edp ||

sys/dev/pci/drm/display/drm_dsc_helper.c

1460

u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc)

sys/dev/pci/drm/display/drm_dsc_helper.c

1462

return 8 * dsc->rc_model_size / (dsc->rc_model_size - dsc->initial_offset);

sys/dev/pci/drm/display/drm_dsc_helper.c

1472

u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc)

sys/dev/pci/drm/display/drm_dsc_helper.c

1474

return 2 << (dsc->bits_per_component - 8);

sys/dev/pci/drm/i915/display/icl_dsi.c

1509

if (pipe_config->dsc.compressed_bpp_x16) {

sys/dev/pci/drm/i915/display/icl_dsi.c

1510

int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);

sys/dev/pci/drm/i915/display/icl_dsi.c

1618

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/icl_dsi.c

1631

if (crtc_state->dsc.slice_count > 1)

sys/dev/pci/drm/i915/display/icl_dsi.c

1632

crtc_state->dsc.num_streams = 2;

sys/dev/pci/drm/i915/display/icl_dsi.c

1634

crtc_state->dsc.num_streams = 1;

sys/dev/pci/drm/i915/display/icl_dsi.c

1658

crtc_state->dsc.compression_enable = true;

sys/dev/pci/drm/i915/display/icl_dsi.c

1771

if (crtc_state->dsc.compression_enable) {

sys/dev/pci/drm/i915/display/icl_dsi.c

351

if (crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/icl_dsi.c

352

bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

sys/dev/pci/drm/i915/display/icl_dsi.c

748

if (pipe_config->dsc.compression_enable) {

sys/dev/pci/drm/i915/display/icl_dsi.c

893

if (crtc_state->dsc.compression_enable) {

sys/dev/pci/drm/i915/display/icl_dsi.c

894

mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

sys/dev/pci/drm/i915/display/icl_dsi.c

917

if (crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/icl_dsi.c

918

bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

sys/dev/pci/drm/i915/display/intel_audio.c

465

vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;

sys/dev/pci/drm/i915/display/intel_audio.c

532

if (crtc_state->dsc.compression_enable &&

sys/dev/pci/drm/i915/display/intel_bios.c

2178

devdata->dsc = kmemdup(&params->data[index],

sys/dev/pci/drm/i915/display/intel_bios.c

2179

sizeof(*devdata->dsc), GFP_KERNEL);

sys/dev/pci/drm/i915/display/intel_bios.c

2694

devdata->dsc != NULL);

sys/dev/pci/drm/i915/display/intel_bios.c

3298

kfree(devdata->dsc);

sys/dev/pci/drm/i915/display/intel_bios.c

3497

struct dsc_compression_parameters_entry *dsc,

sys/dev/pci/drm/i915/display/intel_bios.c

3501

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_bios.c

3504

vdsc_cfg->dsc_version_major = dsc->version_major;

sys/dev/pci/drm/i915/display/intel_bios.c

3505

vdsc_cfg->dsc_version_minor = dsc->version_minor;

sys/dev/pci/drm/i915/display/intel_bios.c

3507

if (dsc->support_12bpc && dsc_max_bpc >= 12)

sys/dev/pci/drm/i915/display/intel_bios.c

3509

else if (dsc->support_10bpc && dsc_max_bpc >= 10)

sys/dev/pci/drm/i915/display/intel_bios.c

3511

else if (dsc->support_8bpc && dsc_max_bpc >= 8)

sys/dev/pci/drm/i915/display/intel_bios.c

3519

crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp,

sys/dev/pci/drm/i915/display/intel_bios.c

3520

VBT_DSC_MAX_BPP(dsc->max_bpp)));

sys/dev/pci/drm/i915/display/intel_bios.c

3528

if (dsc->slices_per_line & BIT(2)) {

sys/dev/pci/drm/i915/display/intel_bios.c

3529

crtc_state->dsc.slice_count = 4;

sys/dev/pci/drm/i915/display/intel_bios.c

3530

} else if (dsc->slices_per_line & BIT(1)) {

sys/dev/pci/drm/i915/display/intel_bios.c

3531

crtc_state->dsc.slice_count = 2;

sys/dev/pci/drm/i915/display/intel_bios.c

3534

if (!(dsc->slices_per_line & BIT(0)))

sys/dev/pci/drm/i915/display/intel_bios.c

3538

crtc_state->dsc.slice_count = 1;

sys/dev/pci/drm/i915/display/intel_bios.c

3542

crtc_state->dsc.slice_count != 0)

sys/dev/pci/drm/i915/display/intel_bios.c

3546

crtc_state->dsc.slice_count);

sys/dev/pci/drm/i915/display/intel_bios.c

3552

vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,

sys/dev/pci/drm/i915/display/intel_bios.c

3553

dsc->rc_buffer_size);

sys/dev/pci/drm/i915/display/intel_bios.c

3556

vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);

sys/dev/pci/drm/i915/display/intel_bios.c

3558

vdsc_cfg->block_pred_enable = dsc->block_prediction_enable;

sys/dev/pci/drm/i915/display/intel_bios.c

3560

vdsc_cfg->slice_height = dsc->slice_height;

sys/dev/pci/drm/i915/display/intel_bios.c

3578

if (!devdata->dsc)

sys/dev/pci/drm/i915/display/intel_bios.c

3581

fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);

sys/dev/pci/drm/i915/display/intel_bios.c

76

struct dsc_compression_parameters_entry *dsc;

sys/dev/pci/drm/i915/display/intel_display.c

1979

if (crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_display.c

5394

PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);

sys/dev/pci/drm/i915/display/intel_display.c

5395

PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);

sys/dev/pci/drm/i915/display/intel_display.c

5396

PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);

sys/dev/pci/drm/i915/display/intel_display.c

5397

PIPE_CONF_CHECK_BOOL(dsc.config.native_422);

sys/dev/pci/drm/i915/display/intel_display.c

5398

PIPE_CONF_CHECK_BOOL(dsc.config.native_420);

sys/dev/pci/drm/i915/display/intel_display.c

5399

PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);

sys/dev/pci/drm/i915/display/intel_display.c

5400

PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);

sys/dev/pci/drm/i915/display/intel_display.c

5401

PIPE_CONF_CHECK_I(dsc.config.bits_per_component);

sys/dev/pci/drm/i915/display/intel_display.c

5402

PIPE_CONF_CHECK_I(dsc.config.pic_width);

sys/dev/pci/drm/i915/display/intel_display.c

5403

PIPE_CONF_CHECK_I(dsc.config.pic_height);

sys/dev/pci/drm/i915/display/intel_display.c

5404

PIPE_CONF_CHECK_I(dsc.config.slice_width);

sys/dev/pci/drm/i915/display/intel_display.c

5405

PIPE_CONF_CHECK_I(dsc.config.slice_height);

sys/dev/pci/drm/i915/display/intel_display.c

5406

PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);

sys/dev/pci/drm/i915/display/intel_display.c

5407

PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);

sys/dev/pci/drm/i915/display/intel_display.c

5408

PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);

sys/dev/pci/drm/i915/display/intel_display.c

5409

PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);

sys/dev/pci/drm/i915/display/intel_display.c

541

new_crtc_state->dsc.compression_enable) {

sys/dev/pci/drm/i915/display/intel_display.c

5410

PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);

sys/dev/pci/drm/i915/display/intel_display.c

5411

PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5412

PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);

sys/dev/pci/drm/i915/display/intel_display.c

5413

PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);

sys/dev/pci/drm/i915/display/intel_display.c

5414

PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5415

PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5416

PIPE_CONF_CHECK_I(dsc.config.initial_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5417

PIPE_CONF_CHECK_I(dsc.config.final_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5418

PIPE_CONF_CHECK_I(dsc.config.rc_model_size);

sys/dev/pci/drm/i915/display/intel_display.c

5419

PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);

sys/dev/pci/drm/i915/display/intel_display.c

5420

PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);

sys/dev/pci/drm/i915/display/intel_display.c

5421

PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);

sys/dev/pci/drm/i915/display/intel_display.c

5422

PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5423

PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);

sys/dev/pci/drm/i915/display/intel_display.c

5425

PIPE_CONF_CHECK_BOOL(dsc.compression_enable);

sys/dev/pci/drm/i915/display/intel_display.c

5426

PIPE_CONF_CHECK_I(dsc.num_streams);

sys/dev/pci/drm/i915/display/intel_display.c

5427

PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);

sys/dev/pci/drm/i915/display/intel_display.c

595

old_crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

1023

seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);

sys/dev/pci/drm/i915/display/intel_display_debugfs.c

927

str_yes_no(crtc_state->dsc.compression_enable));

sys/dev/pci/drm/i915/display/intel_display_types.h

1278

} dsc;

sys/dev/pci/drm/i915/display/intel_dp.c

1426

bool dsc = false;

sys/dev/pci/drm/i915/display/intel_dp.c

1509

dsc = dsc_max_compressed_bpp && dsc_slice_count;

sys/dev/pci/drm/i915/display/intel_dp.c

1512

if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)

sys/dev/pci/drm/i915/display/intel_dp.c

1515

if (mode_rate > max_rate && !dsc)

sys/dev/pci/drm/i915/display/intel_dp.c

1888

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_dp.c

2202

pipe_config->dsc.compressed_bpp_x16 = bpp_x16;

sys/dev/pci/drm/i915/display/intel_dp.c

2335

pipe_config->dsc.compressed_bpp_x16 =

sys/dev/pci/drm/i915/display/intel_dp.c

2403

pipe_config->dsc.slice_count =

sys/dev/pci/drm/i915/display/intel_dp.c

2406

if (!pipe_config->dsc.slice_count) {

sys/dev/pci/drm/i915/display/intel_dp.c

2409

pipe_config->dsc.slice_count);

sys/dev/pci/drm/i915/display/intel_dp.c

2426

pipe_config->dsc.slice_count = dsc_dp_slice_count;

sys/dev/pci/drm/i915/display/intel_dp.c

2436

pipe_config->dsc.slice_count == 12)

sys/dev/pci/drm/i915/display/intel_dp.c

2437

pipe_config->dsc.num_streams = 3;

sys/dev/pci/drm/i915/display/intel_dp.c

2438

else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)

sys/dev/pci/drm/i915/display/intel_dp.c

2439

pipe_config->dsc.num_streams = 2;

sys/dev/pci/drm/i915/display/intel_dp.c

2441

pipe_config->dsc.num_streams = 1;

sys/dev/pci/drm/i915/display/intel_dp.c

2449

FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));

sys/dev/pci/drm/i915/display/intel_dp.c

2453

pipe_config->dsc.compression_enable = true;

sys/dev/pci/drm/i915/display/intel_dp.c

2457

FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),

sys/dev/pci/drm/i915/display/intel_dp.c

2458

pipe_config->dsc.slice_count);

sys/dev/pci/drm/i915/display/intel_dp.c

2471

bool dsc,

sys/dev/pci/drm/i915/display/intel_dp.c

2484

if (!dsc) {

sys/dev/pci/drm/i915/display/intel_dp.c

2517

str_on_off(dsc),

sys/dev/pci/drm/i915/display/intel_dp.c

2557

bool dsc,

sys/dev/pci/drm/i915/display/intel_dp.c

2589

if (!dsc && intel_dp_in_hdr_mode(conn_state)) {

sys/dev/pci/drm/i915/display/intel_dp.c

2602

if (dsc && !intel_dp_dsc_compute_pipe_bpp_limits(connector, limits))

sys/dev/pci/drm/i915/display/intel_dp.c

2626

dsc,

sys/dev/pci/drm/i915/display/intel_dp.c

2634

int bpp = crtc_state->dsc.compression_enable ?

sys/dev/pci/drm/i915/display/intel_dp.c

2635

fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :

sys/dev/pci/drm/i915/display/intel_dp.c

2735

FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),

sys/dev/pci/drm/i915/display/intel_dp.c

3194

if (crtc_state->dsc.compression_enable) {

sys/dev/pci/drm/i915/display/intel_dp.c

3205

if (crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_dp.c

3206

link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;

sys/dev/pci/drm/i915/display/intel_dp.c

3242

(crtc_state->dsc.compression_enable &&

sys/dev/pci/drm/i915/display/intel_dp.c

3244

crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8)));

sys/dev/pci/drm/i915/display/intel_dp.c

3316

if (pipe_config->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_dp.c

3317

link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;

sys/dev/pci/drm/i915/display/intel_dp.c

3567

if (!new_crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_dp.c

3598

if (!old_crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_dp.c

3773

if (crtc_state->dsc.compression_enable) {

sys/dev/pci/drm/i915/display/intel_dp.c

6149

if (crtc_state && crtc_state->dsc.compression_enable) {

sys/dev/pci/drm/i915/display/intel_dp.h

199

bool dsc,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

143

bool dsc)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1462

bool dsc = false;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

149

if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1544

dsc = dsc_max_compressed_bpp && dsc_slice_count;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1547

if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

1552

if (mode_rate > max_rate && !dsc) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

2054

if (old_crtc_state->dsc.compression_enable ==

sys/dev/pci/drm/i915/display/intel_dp_mst.c

2055

new_crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

260

int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

275

drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) ||

sys/dev/pci/drm/i915/display/intel_dp_mst.c

296

if (dsc) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

303

max_dpt_bpp_x16 = fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc));

sys/dev/pci/drm/i915/display/intel_dp_mst.c

313

if (dsc) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

330

if (dsc && !intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

336

link_bpp_x16 = dsc ? bpp_x16 :

sys/dev/pci/drm/i915/display/intel_dp_mst.c

430

if (!dsc)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

433

crtc_state->dsc.compressed_bpp_x16 = bpp_x16;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

436

slots, FXP_Q4_ARGS(bpp_x16), dsc);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

557

bool dsc)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

566

if (!dsc) {

sys/dev/pci/drm/i915/display/intel_dp_mst.c

616

bool dsc,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

623

crtc_state, false, dsc,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

631

dsc);

sys/dev/pci/drm/i915/display/intel_dp_mst.h

37

int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc);

sys/dev/pci/drm/i915/display/intel_link_bw.c

122

if (crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_link_bw.c

123

link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;

sys/dev/pci/drm/i915/display/intel_psr.c

1272

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_psr.c

1303

if (crtc_state->dsc.compression_enable &&

sys/dev/pci/drm/i915/display/intel_psr.c

1458

if (crtc_state->dsc.compression_enable &&

sys/dev/pci/drm/i915/display/intel_psr.c

2495

if (!crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_psr.c

2573

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_psr.c

2578

if (crtc_state->dsc.compression_enable &&

sys/dev/pci/drm/i915/display/intel_vdsc.c

1024

crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;

sys/dev/pci/drm/i915/display/intel_vdsc.c

1025

if (!crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_vdsc.c

1029

crtc_state->dsc.num_streams = 3;

sys/dev/pci/drm/i915/display/intel_vdsc.c

1031

crtc_state->dsc.num_streams = 2;

sys/dev/pci/drm/i915/display/intel_vdsc.c

1033

crtc_state->dsc.num_streams = 1;

sys/dev/pci/drm/i915/display/intel_vdsc.c

1045

FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),

sys/dev/pci/drm/i915/display/intel_vdsc.c

1046

crtc_state->dsc.slice_count,

sys/dev/pci/drm/i915/display/intel_vdsc.c

1047

crtc_state->dsc.num_streams);

sys/dev/pci/drm/i915/display/intel_vdsc.c

1053

if (!crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_vdsc.c

1057

drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);

sys/dev/pci/drm/i915/display/intel_vdsc.c

1066

if (!crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_vdsc.c

1095

(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *

sys/dev/pci/drm/i915/display/intel_vdsc.c

265

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

275

struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

276

u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);

sys/dev/pci/drm/i915/display/intel_vdsc.c

282

pipe_config->dsc.slice_count);

sys/dev/pci/drm/i915/display/intel_vdsc.c

307

vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;

sys/dev/pci/drm/i915/display/intel_vdsc.c

403

return crtc_state->dsc.num_streams;

sys/dev/pci/drm/i915/display/intel_vdsc.c

458

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

714

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

720

if (!crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_vdsc.c

737

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

740

if (!crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_vdsc.c

759

const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

795

if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {

sys/dev/pci/drm/i915/display/intel_vdsc.c

814

if (!crtc_state->dsc.compression_enable)

sys/dev/pci/drm/i915/display/intel_vdsc.c

852

if (old_crtc_state->dsc.compression_enable ||

sys/dev/pci/drm/i915/display/intel_vdsc.c

903

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

sys/dev/pci/drm/i915/display/intel_vdsc.c

927

crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;

sys/dev/pci/drm/i915/display/skl_watermark.c

2191

if (!crtc_state->dsc.compression_enable ||

sys/dev/pci/drm/include/drm/display/drm_dsc_helper.h

30

u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);

sys/dev/pci/drm/include/drm/display/drm_dsc_helper.h

31

u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);

sys/dev/pci/if_ne_pci.c

166

struct dp8390_softc *dsc = &nsc->sc_dp8390;

sys/dev/pci/if_ne_pci.c

198

dsc->sc_regt = nict;

sys/dev/pci/if_ne_pci.c

199

dsc->sc_regh = nich;

sys/dev/pci/if_ne_pci.c

205

dsc->sc_enabled = 1;

sys/dev/pci/if_ne_pci.c

207

dsc->sc_mediachange = npp->npp_mediachange;

sys/dev/pci/if_ne_pci.c

208

dsc->sc_mediastatus = npp->npp_mediastatus;

sys/dev/pci/if_ne_pci.c

209

dsc->sc_media_init = npp->npp_media_init;

sys/dev/pci/if_ne_pci.c

210

dsc->init_card = npp->npp_init_card;

sys/dev/pci/if_ne_pci.c

219

psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dp8390_intr, dsc,

sys/dev/pci/if_ne_pci.c

220

dsc->sc_dev.dv_xname);

sys/dev/pcmcia/if_ne_pcmcia.c

1000

dsc->sc_dev.dv_xname);

sys/dev/pcmcia/if_ne_pcmcia.c

1007

dsc->sc_dev.dv_xname);

sys/dev/pcmcia/if_ne_pcmcia.c

607

struct dp8390_softc *dsc = &nsc->sc_dp8390;

sys/dev/pcmcia/if_ne_pcmcia.c

677

dsc->sc_regt = psc->sc_pcioh.iot;

sys/dev/pcmcia/if_ne_pcmcia.c

678

dsc->sc_regh = psc->sc_pcioh.ioh;

sys/dev/pcmcia/if_ne_pcmcia.c

681

if (bus_space_subregion(dsc->sc_regt, dsc->sc_regh,

sys/dev/pcmcia/if_ne_pcmcia.c

689

dsc->sc_enable = ne_pcmcia_enable;

sys/dev/pcmcia/if_ne_pcmcia.c

690

dsc->sc_disable = ne_pcmcia_disable;

sys/dev/pcmcia/if_ne_pcmcia.c

700

dsc->sc_enabled = 1;

sys/dev/pcmcia/if_ne_pcmcia.c

759

dsc->sc_mediachange = ax88190_mediachange;

sys/dev/pcmcia/if_ne_pcmcia.c

760

dsc->sc_mediastatus = ax88190_mediastatus;

sys/dev/pcmcia/if_ne_pcmcia.c

761

dsc->init_card = ax88190_init_card;

sys/dev/pcmcia/if_ne_pcmcia.c

762

dsc->stop_card = ax88190_stop_card;

sys/dev/pcmcia/if_ne_pcmcia.c

763

dsc->sc_media_init = ax88190_media_init;

sys/dev/pcmcia/if_ne_pcmcia.c

764

dsc->sc_media_fini = ax88190_media_fini;

sys/dev/pcmcia/if_ne_pcmcia.c

772

bus_space_write_1(dsc->sc_regt, dsc->sc_regh, ED_P0_CR,

sys/dev/pcmcia/if_ne_pcmcia.c

774

if (bus_space_read_1(dsc->sc_regt, dsc->sc_regh, NERTL_RTL0_8019ID0)

sys/dev/pcmcia/if_ne_pcmcia.c

776

bus_space_read_1(dsc->sc_regt, dsc->sc_regh, NERTL_RTL0_8019ID1)

sys/dev/pcmcia/if_ne_pcmcia.c

778

dsc->sc_mediachange = rtl80x9_mediachange;

sys/dev/pcmcia/if_ne_pcmcia.c

779

dsc->sc_mediastatus = rtl80x9_mediastatus;

sys/dev/pcmcia/if_ne_pcmcia.c

780

dsc->init_card = rtl80x9_init_card;

sys/dev/pcmcia/if_ne_pcmcia.c

781

dsc->sc_media_init = rtl80x9_media_init;

sys/dev/pcmcia/if_ne_pcmcia.c

786

dsc->sc_mediachange = dl10019_mediachange;

sys/dev/pcmcia/if_ne_pcmcia.c

787

dsc->sc_mediastatus = dl10019_mediastatus;

sys/dev/pcmcia/if_ne_pcmcia.c

788

dsc->init_card = dl10019_init_card;

sys/dev/pcmcia/if_ne_pcmcia.c

789

dsc->stop_card = dl10019_stop_card;

sys/dev/pcmcia/if_ne_pcmcia.c

790

dsc->sc_media_init = dl10019_media_init;

sys/dev/pcmcia/if_ne_pcmcia.c

791

dsc->sc_media_fini = dl10019_media_fini;

sys/dev/pcmcia/if_ne_pcmcia.c

796

dsc, dsc->sc_dev.dv_xname);

sys/dev/pcmcia/if_ne_pcmcia.c

896

ne_pcmcia_enable(struct dp8390_softc *dsc)

sys/dev/pcmcia/if_ne_pcmcia.c

898

struct ne_pcmcia_softc *psc = (struct ne_pcmcia_softc *)dsc;

sys/dev/pcmcia/if_ne_pcmcia.c

902

dsc, dsc->sc_dev.dv_xname);

sys/dev/pcmcia/if_ne_pcmcia.c

905

dsc->sc_dev.dv_xname);

sys/dev/pcmcia/if_ne_pcmcia.c

913

ne_pcmcia_disable(struct dp8390_softc *dsc)

sys/dev/pcmcia/if_ne_pcmcia.c

915

struct ne_pcmcia_softc *psc = (struct ne_pcmcia_softc *)dsc;

sys/dev/pcmcia/if_ne_pcmcia.c

927

struct dp8390_softc *dsc = &nsc->sc_dp8390;

sys/dev/pcmcia/if_ne_pcmcia.c

938

dsc->sc_dev.dv_xname);

sys/dev/pcmcia/if_ne_pcmcia.c

944

dsc->sc_dev.dv_xname);

sys/dev/pcmcia/if_ne_pcmcia.c

993

struct dp8390_softc *dsc = &nsc->sc_dp8390;

sys/dev/sbus/bpp.c

123

struct bpp_softc *dsc = (void *)self;

sys/dev/sbus/bpp.c

124

struct lsi64854_softc *sc = &dsc->sc_lsi64854;

sys/dev/sbus/bpp.c

179

sc->sc_intrchainarg = dsc;

sys/dev/sbus/bpp.c

184

dsc->sc_bufsz = 1024;

sys/dev/sbus/bpp.c

185

dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT);

sys/dev/sbus/bpp.c

190

struct hwstate *hw = &dsc->sc_hwstate;

sys/dev/sbus/dma_sbus.c

143

struct dma_softc *dsc = (void *)self;

sys/dev/sbus/dma_sbus.c

144

struct lsi64854_softc *sc = &dsc->sc_lsi64854;

sys/dev/sbus/dma_sbus.c

220

sbt = dma_alloc_bustag(dsc);