drm_dp_dpcd_writeb
error = drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_SET_POWER, value);
drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
drm_dp_dpcd_writeb(dp_info->aux,
drm_dp_dpcd_writeb(dp_info->aux,
drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
drm_dp_dpcd_writeb(dp_info->aux,
drm_dp_dpcd_writeb(dp_info->aux,
ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
int ret = drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, val);
drm_dp_dpcd_writeb(aux,
drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT,
err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);
drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,
drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
if (drm_dp_dpcd_writeb(&intel_dp->aux,
if (drm_dp_dpcd_writeb(&intel_dp->aux,
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
if (drm_dp_dpcd_writeb(&intel_dp->aux,
drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1)
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
drm_dp_dpcd_writeb(&intel_dp->aux,
drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
drm_dp_dpcd_writeb(&intel_dp->aux,
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
drm_dp_dpcd_writeb(dp_info->aux,
drm_dp_dpcd_writeb(dp_info->aux,
drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
drm_dp_dpcd_writeb(dp_info->aux,
drm_dp_dpcd_writeb(dp_info->aux,