drm_dp_dpcd_readb
error = drm_dp_dpcd_readb(&sc->sc_dpaux, DP_SET_POWER, &value);
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
ret = drm_dp_dpcd_readb(aux, DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST, &val);
ret = drm_dp_dpcd_readb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &val);
err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
drm_dp_dpcd_readb(&intel_dp->aux,
err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
return drm_dp_dpcd_readb(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0,
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
if (drm_dp_dpcd_readb(&intel_dp->aux,
if (drm_dp_dpcd_readb(&intel_dp->aux,
if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {
ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);
ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status);
ret = drm_dp_dpcd_readb(intel_dp->mst.mgr.aux, DP_MSTM_CTRL, &val);
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
ret = drm_dp_dpcd_readb(aux, offset, status);
ret = drm_dp_dpcd_readb(aux, offset, error_status);
r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
if (drm_dp_dpcd_readb(&intel_dp->aux,
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)