CG_FDO_CTRL2
CG_FDO_CTRL2, FDO_PWM_MODE);
CG_FDO_CTRL2, TMIN);
CG_FDO_CTRL2, TMIN, 0);
CG_FDO_CTRL2, FDO_PWM_MODE, mode);
CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
CG_FDO_CTRL2, TMIN, hwmgr->tmin);
CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28);
CG_FDO_CTRL2, FDO_PWM_MODE);
CG_FDO_CTRL2, TMIN);
CG_FDO_CTRL2, TMIN, 0));
CG_FDO_CTRL2, FDO_PWM_MODE, mode));
CG_FDO_CTRL2, FDO_PWM_MODE,
CG_FDO_CTRL2, TMIN,
CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
CG_FDO_CTRL2, TMIN, 0));
CG_FDO_CTRL2, FDO_PWM_MODE, mode));
CG_FDO_CTRL2, TMIN, 0));
CG_FDO_CTRL2, FDO_PWM_MODE, mode));
CG_FDO_CTRL2, TMIN, 0));
CG_FDO_CTRL2, FDO_PWM_MODE, mode));
CG_FDO_CTRL2, TMIN, 0));
CG_FDO_CTRL2, FDO_PWM_MODE, mode));
tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
WREG32_SMC(CG_FDO_CTRL2, tmp);
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
WREG32_SMC(CG_FDO_CTRL2, tmp);
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
WREG32_SMC(CG_FDO_CTRL2, tmp);
tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
WREG32_SMC(CG_FDO_CTRL2, tmp);
tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
WREG32_SMC(CG_FDO_CTRL2, tmp);
tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
WREG32(CG_FDO_CTRL2, tmp);
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
WREG32(CG_FDO_CTRL2, tmp);
tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
WREG32(CG_FDO_CTRL2, tmp);
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
WREG32(CG_FDO_CTRL2, tmp);
tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
WREG32(CG_FDO_CTRL2, tmp);