sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

457

display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

4588

display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

460

display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,

sys/dev/pci/drm/radeon/ci_dpm.c

1945

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/ci_dpm.c

1957

WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/pci/drm/radeon/ci_dpm.c

2006

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/ci_dpm.c

2012

WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/pci/drm/radeon/cypress_dpm.c

1733

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/cypress_dpm.c

1742

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/pci/drm/radeon/cypress_dpm.c

1750

tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);

sys/dev/pci/drm/radeon/cypress_dpm.c

1761

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1182

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1195

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/pci/drm/radeon/rv6xx_dpm.c

989

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/pci/drm/radeon/rv770_dpm.c

1345

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/rv770_dpm.c

1358

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/pci/drm/radeon/rv770_dpm.c

881

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/rv770_dpm.c

886

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/pci/drm/radeon/si_dpm.c

3629

tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);

sys/dev/pci/drm/radeon/si_dpm.c

3640

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/pci/drm/radeon/si_dpm.c

3743

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

sys/dev/pci/drm/radeon/si_dpm.c

3752

WREG32(CG_DISPLAY_GAP_CNTL, tmp);