bin/ksh/eval.c

1180

maybe_expand_tilde(char *p, XString *dsp, char **dpp, int isassign)

bin/ksh/eval.c

1183

char *dp = *dpp;

bin/ksh/eval.c

1205

*dpp = dp;

sbin/mountd/mountd.c

1496

add_expdir(struct dirlist **dpp, char *cp, int len)

sbin/mountd/mountd.c

1504

dp->dp_left = *dpp;

sbin/mountd/mountd.c

1509

*dpp = dp;

sbin/mountd/mountd.c

1556

add_dlist(struct dirlist **dpp, struct dirlist *newdp, struct grouplist *grp,

sbin/mountd/mountd.c

1563

dp = *dpp;

sbin/mountd/mountd.c

1577

*dpp = dp;

sys/arch/amd64/stand/efiboot/efiboot.c

678

EFI_DEV_PATH_PTR dpp;

sys/arch/amd64/stand/efiboot/efiboot.c

710

dpp = (EFI_DEV_PATH_PTR)dp;

sys/arch/amd64/stand/efiboot/efiboot.c

713

if (dpp.Acpi->HID == EFI_PNP_ID(0x0501)) {

sys/arch/amd64/stand/efiboot/efiboot.c

714

uid = dpp.Acpi->UID;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9622

adev->dm.dc->caps.color.dpp.gamma_corr)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

823

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

770

is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1390

adev->dm.dc->caps.color.dpp.gamma_corr)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1615

struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

169

pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

170

pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

325

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

326

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

327

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

332

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

293

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

294

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

295

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

300

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

317

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

567

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

568

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

569

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

574

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1034

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1040

if (dpp && dpp->funcs->dpp_setup) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1042

dpp->funcs->dpp_setup(dpp,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1050

if (dpp && dpp->funcs->set_cursor_matrix) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1051

dpp->funcs->set_cursor_matrix(dpp,

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1060

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1065

if (dpp->funcs->dpp_program_bias_and_scale) {

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

1066

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1541

if (pipe_ctx->plane_res.dpp != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1542

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1543

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1553

if (pipe_ctx->plane_res.dpp != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1554

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1555

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1568

if (pipe_ctx->plane_res.dpp != NULL)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1569

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

1570

pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2315

pipe->plane_res.dpp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2331

pipe->plane_res.dpp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2337

pipe->plane_res.dpp->inst,

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2343

pipe->plane_res.dpp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2348

pipe->plane_res.dpp->inst);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

2544

split_pipe->plane_res.dpp = pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3695

pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3840

pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5464

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

942

if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

946

*dpp_offset *= pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

381

(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

382

(!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))

sys/dev/pci/drm/amd/display/dc/dc.h

264

struct dpp_color_caps dpp;

sys/dev/pci/drm/amd/display/dc/dc.h

777

bool dpp: 1;

sys/dev/pci/drm/amd/display/dc/dc.h

797

bool dpp : 1; /* Display pipes and planes */

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1054

const struct hubp *hubp, const struct dpp *dpp)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1063

pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1069

const struct hubp *hubp, const struct dpp *dpp)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1079

pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1124

pCtx->plane_res.hubp, pCtx->plane_res.dpp);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1134

pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1188

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

371

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)

sys/dev/pci/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

397

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

343

if (pipe_ctx->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

344

copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

153

if (pipe_ctx->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c

154

copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

343

struct dpp *dpp = pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

346

dpp->funcs->dpp_read_state(dpp, &s);

sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

353

dpp->inst, s.igam_input_format,

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

318

if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

333

input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c

540

secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1891

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

465

} dpp;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13106

out->informative.dpp.total_num_dpps_required = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13109

out->informative.dpp.total_num_dpps_required += mode_lib->mp.NoOfDPP[k];

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

125

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

131

dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

137

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

138

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

174

if (!dpp->ctx->dc->debug.always_scale) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

188

void dpp_reset(struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

190

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

192

dpp->filter_h_c = NULL;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

193

dpp->filter_v_c = NULL;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

194

dpp->filter_h = NULL;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

195

dpp->filter_v = NULL;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

200

memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

201

memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

207

struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

209

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

223

re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

224

if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

228

dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

230

if (dpp->is_write_to_ram_a_safe)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

237

dpp->pwl_data = *params;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

239

re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

240

dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

263

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

266

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

278

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

291

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

414

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

418

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

42

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

435

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

441

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

45

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

49

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

494

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

497

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

506

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

510

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

513

if (dpp->tf_mask->DPPCLK_RATE_CONTROL)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

523

void dpp_force_disable_cursor(struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

525

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

573

struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

580

dpp->base.ctx = ctx;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

582

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

583

dpp->base.funcs = &dcn10_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

584

dpp->base.caps = &dcn10_dpp_cap;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

586

dpp->tf_regs = tf_regs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

587

dpp->tf_shift = tf_shift;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

588

dpp->tf_mask = tf_mask;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

590

dpp->lb_pixel_depth_supported =

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

596

dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

597

dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

94

void dpp_read_state(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

97

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1358

struct dpp base;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1383

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1387

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1394

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1409

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1413

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1417

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1421

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1427

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1431

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1437

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1441

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1444

void dpp1_full_bypass(struct dpp *dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1447

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1450

void dpp1_set_degamma_pwl(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1454

void dpp_read_state(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1457

void dpp_reset(struct dpp *dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1460

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1465

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1469

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1474

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1479

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1482

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1486

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1490

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1494

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1498

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1506

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1511

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1515

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1526

void dpp1_cm_get_gamut_remap(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1528

void dpp_force_disable_cursor(struct dpp *dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

30

#define TO_DCN10_DPP(dpp)\

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

31

container_of(dpp, struct dcn10_dpp, base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

118

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

119

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

120

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

121

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

129

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

139

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

149

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

161

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

164

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

169

program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

180

program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

184

static void read_gamut_remap(struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

196

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

197

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

198

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

199

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

207

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

217

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

227

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

233

void dpp1_cm_get_gamut_remap(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

236

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

240

read_gamut_remap(dpp, arr_reg_val, &select);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

253

struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

281

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

282

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

283

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

284

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

299

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

308

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

311

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

321

dpp1_cm_program_color_matrix(dpp, regval);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

325

struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

328

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

329

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

330

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

331

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

332

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

333

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

334

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

335

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

337

reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

338

reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

339

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

340

reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

341

reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

342

reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

343

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

344

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

345

reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

346

reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

347

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

348

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

352

struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

355

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

356

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

357

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

358

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

359

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

360

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

361

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

362

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

364

reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

365

reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

366

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

367

reg->masks.field_region_end_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

368

reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

369

reg->masks.field_region_end_base = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

370

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

371

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

372

reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

373

reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

374

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

375

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

378

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

381

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

383

dpp1_cm_program_color_matrix(dpp, regval);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

386

void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

389

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

396

void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

401

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

420

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

423

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

43

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

434

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

437

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

440

dpp1_cm_get_reg_field(dpp, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

457

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

46

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

463

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

466

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

469

dpp1_cm_get_reg_field(dpp, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

486

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

490

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

495

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

50

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

538

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

539

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

540

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

541

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

556

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

566

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

569

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

587

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

590

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

593

dpp1_cm_get_degamma_reg_field(dpp, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

611

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

616

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

619

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

622

dpp1_cm_get_degamma_reg_field(dpp, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

639

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

643

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

646

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

654

struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

656

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

663

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

666

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

690

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

693

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

703

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

708

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

724

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

731

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

753

void dpp1_set_degamma_pwl(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

771

void dpp1_full_bypass(struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

773

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

786

if (dpp->tf_mask->CM_BYPASS_EN)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

795

static bool dpp1_ingamma_ram_inuse(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

800

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

827

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

831

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

876

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

879

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

92

struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

124

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

158

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

161

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

163

if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

168

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

169

dpp->base.ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

170

dpp->base.deferred_reg_writes.bits.disable_dscl = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

180

struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

187

if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

207

if (dpp->base.caps->max_lb_partitions == 31)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

241

struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

279

struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

321

filter_updated = (filter_h && (filter_h != dpp->filter_h))

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

322

|| (filter_v && (filter_v != dpp->filter_v));

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

329

filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

330

|| (filter_v_c && (filter_v_c != dpp->filter_v_c));

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

338

dpp, scl_data->taps.h_taps,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

341

dpp->filter_h = filter_h;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

344

dpp, scl_data->taps.v_taps,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

347

dpp->filter_v = filter_v;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

351

dpp, scl_data->taps.h_taps_c,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

356

dpp, scl_data->taps.v_taps_c,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

360

dpp->filter_h_c = filter_h_c;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

361

dpp->filter_v_c = filter_v_c;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

364

scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

365

dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

44

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

459

static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

468

if (dpp->base.ctx->dc->debug.use_max_lb) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

47

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

475

dpp->base.caps->dscl_calc_lb_num_partitions(

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

482

dpp->base.caps->dscl_calc_lb_num_partitions(

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

491

dpp->base.caps->dscl_calc_lb_num_partitions(

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

499

dpp->base.caps->dscl_calc_lb_num_partitions(

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

51

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

511

struct dcn10_dpp *dpp, const struct scaler_data *data)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

587

static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

613

void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

617

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

623

if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

628

dpp->scl_data = *scl_data;

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

646

dpp1_dscl_set_recout(dpp, &scl_data->recout);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

665

lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

666

dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

685

dpp1_dscl_set_manual_ratio_init(dpp, scl_data);

sys/dev/pci/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

694

dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

105

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

317

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

320

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

340

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

344

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

369

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

407

struct dcn20_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

414

dpp->base.ctx = ctx;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

416

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

417

dpp->base.funcs = &dcn20_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

418

dpp->base.caps = &dcn20_dpp_cap;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

42

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

420

dpp->tf_regs = tf_regs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

421

dpp->tf_shift = tf_shift;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

422

dpp->tf_mask = tf_mask;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

424

dpp->lb_pixel_depth_supported =

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

430

dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

431

dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

45

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

49

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

51

void dpp20_read_state(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

54

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

78

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

81

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

93

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

98

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

29

#define TO_DCN20_DPP(dpp)\

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

30

container_of(dpp, struct dcn20_dpp, base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

678

struct dpp base;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

709

void dpp20_read_state(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

713

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

717

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

721

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

725

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

731

struct dpp *dpp_base, const struct pwl_params *params);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

734

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

738

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

742

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

759

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

763

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

767

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

772

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

783

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

786

void dpp2_cm_get_gamut_remap(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1014

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1020

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1035

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1039

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1050

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1055

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1084

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1089

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1105

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1108

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1116

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

117

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1196

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1199

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

135

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

138

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

162

struct dcn20_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

189

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

190

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

191

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

192

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

203

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

214

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

217

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

222

program_gamut_remap(dpp, NULL, DCN2_GAMUT_REMAP_BYPASS);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

233

program_gamut_remap(dpp, arr_reg_val, DCN2_GAMUT_REMAP_COEF_A);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

237

static void read_gamut_remap(struct dcn20_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

250

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

251

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

252

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

253

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

259

cm_helper_read_color_matrices(dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

267

cm_helper_read_color_matrices(dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

273

void dpp2_cm_get_gamut_remap(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

276

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

280

read_gamut_remap(dpp, arr_reg_val, &select);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

293

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

298

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

339

icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

340

icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

341

icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

342

icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

357

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

366

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

369

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

37

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

377

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

380

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

390

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

395

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

414

struct dcn20_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

417

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

418

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

419

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

420

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

421

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

422

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

423

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

424

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

426

reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

427

reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

428

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

429

reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

43

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

430

reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

431

reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

432

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

433

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

434

reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

435

reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

436

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

437

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

442

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

445

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

448

dcn20_dpp_cm_get_reg_field(dpp, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

465

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

47

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

470

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

473

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

476

dcn20_dpp_cm_get_reg_field(dpp, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

493

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

496

static enum dc_lut_mode dpp20_get_blndgam_current(struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

500

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

51

struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

523

struct dpp *dpp_base, const struct pwl_params *params)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

527

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

53

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

558

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

566

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

589

static enum dc_lut_mode dpp20_get_shaper_current(struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

593

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

616

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

619

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

631

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

635

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

65

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

70

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

781

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

785

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

86

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

93

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

932

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

938

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

968

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

974

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

191

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

198

dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

203

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

204

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

251

if (!dpp->ctx->dc->debug.always_scale) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

298

struct dcn201_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

305

dpp->base.ctx = ctx;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

307

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

308

dpp->base.funcs = &dcn201_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

309

dpp->base.caps = &dcn201_dpp_cap;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

311

dpp->tf_regs = tf_regs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

312

dpp->tf_shift = tf_shift;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

313

dpp->tf_mask = tf_mask;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

315

dpp->lb_pixel_depth_supported =

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

320

dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

321

dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

35

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

38

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

42

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

45

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

52

struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

30

#define TO_DCN201_DPP(dpp)\

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

31

container_of(dpp, struct dcn201_dpp, base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

58

struct dpp base;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1043

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1047

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1193

static bool dpp3_program_shaper(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1199

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1234

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1240

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1281

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1287

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1302

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1306

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1317

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1322

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

134

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

135

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1351

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1356

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

136

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

137

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1372

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1375

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1382

static bool dpp3_program_3dlut(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1504

struct dcn3_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1511

dpp->base.ctx = ctx;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1513

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1514

dpp->base.funcs = &dcn30_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1515

dpp->base.caps = &dcn30_dpp_cap;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1517

dpp->tf_regs = tf_regs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1518

dpp->tf_shift = tf_shift;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1519

dpp->tf_mask = tf_mask;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

152

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

162

void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

164

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

205

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

212

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

34

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

37

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

385

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

389

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

41

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

419

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

44

void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

46

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

467

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

468

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

481

dpp->caps->dscl_calc_lb_num_partitions(

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

506

if (!dpp->ctx->dc->debug.always_scale) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

520

static void dpp3_deferred_update(struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

523

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

568

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

571

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

585

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

588

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

602

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

605

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

619

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

622

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

632

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

637

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

668

struct dcn3_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

671

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

672

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

673

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

674

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

675

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

676

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

677

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

678

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

680

reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

681

reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

682

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

683

reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

684

reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

685

reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

686

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

687

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

688

reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

689

reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

690

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

691

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

696

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

699

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

702

dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

719

cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

724

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

727

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

730

dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

747

cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

750

static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

756

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

781

static bool dpp3_program_blnd_lut(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

786

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

820

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

828

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

851

static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

855

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

878

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

881

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

89

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

893

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

897

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

94

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

30

#define TO_DCN30_DPP(dpp)\

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

31

container_of(dpp, struct dcn3_dpp, base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

561

struct dpp base;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

588

struct dpp *dpp_base, const struct pwl_params *params);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

591

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

594

void dpp30_read_state(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

598

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

603

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

611

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

615

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

619

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

622

void dpp3_set_pre_degam(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

626

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

630

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

636

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

640

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

643

void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

127

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

130

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

146

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

149

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

157

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

160

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

169

struct dcn3_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

173

reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

174

reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

175

reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

176

reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

178

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

179

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

180

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

181

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

182

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

183

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

184

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

185

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

187

reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

188

reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

189

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

190

reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

191

reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

192

reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

193

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

194

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

195

reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

196

reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

197

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

198

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

202

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

205

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

216

struct dpp *dpp_base, const struct pwl_params *params)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

220

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

290

dpp3_gamcor_reg_field(dpp, &gam_regs);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

305

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

308

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

315

struct dcn3_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

34

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

341

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

342

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

343

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

344

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

352

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

362

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

37

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

374

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

377

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

383

program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

405

program_gamut_remap(dpp, arr_reg_val, gamut_mode);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

409

static void read_gamut_remap(struct dcn3_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

41

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

421

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

422

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

423

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

424

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

430

cm_helper_read_color_matrices(dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

438

cm_helper_read_color_matrices(dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

44

struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

444

void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

447

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

451

read_gamut_remap(dpp, arr_reg_val, &select);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

46

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

57

static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

62

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

78

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

84

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

147

struct dcn3_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

154

dpp->base.ctx = ctx;

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

156

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

157

dpp->base.funcs = &dcn32_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

158

dpp->base.caps = &dcn32_dpp_cap;

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

160

dpp->tf_regs = tf_regs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

161

dpp->tf_shift = tf_shift;

sys/dev/pci/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

162

dpp->tf_mask = tf_mask;

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

129

struct dcn3_dpp *dpp, struct dc_context *ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

134

bool ret = dpp32_construct(dpp, ctx, inst, tf_regs,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

138

dpp->base.funcs = &dcn35_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

141

if (dpp->base.ctx->asic_id.hw_internal_rev < 0x40)

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

142

dpp->dispclk_r_gate_disable = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

146

void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable)

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

31

#define REG(reg) dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

33

#define CTX dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

37

((const struct dcn35_dpp_shift *)(dpp->tf_shift))->field_name, \

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

38

((const struct dcn35_dpp_mask *)(dpp->tf_mask))->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

41

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

45

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

48

if (dpp->tf_mask->DPPCLK_RATE_CONTROL)

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

53

if (dpp->dispclk_r_gate_disable)

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

61

if (dpp->dispclk_r_gate_disable)

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

71

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

74

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

53

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

62

void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);

sys/dev/pci/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

64

void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

262

struct dcn401_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

269

dpp->base.ctx = ctx;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

271

dpp->base.inst = inst;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

272

dpp->base.funcs = &dcn401_dpp_funcs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

273

dpp->base.caps = &dcn401_dpp_cap;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

275

dpp->tf_regs = tf_regs;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

276

dpp->tf_shift = tf_shift;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

277

dpp->tf_mask = tf_mask;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

36

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

39

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

43

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

45

void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

47

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

56

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

63

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

32

#define TO_DCN401_DPP(dpp)\

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

33

container_of(dpp, struct dcn401_dpp, base)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

658

struct dpp base;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

694

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

698

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

706

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

710

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

717

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

733

void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

736

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

125

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

131

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

142

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

145

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

157

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

161

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

199

cur_matrix_regs.shifts.csc_c11 = dpp->tf_shift->CUR0_MATRIX_C11_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

200

cur_matrix_regs.masks.csc_c11 = dpp->tf_mask->CUR0_MATRIX_C11_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

201

cur_matrix_regs.shifts.csc_c12 = dpp->tf_shift->CUR0_MATRIX_C12_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

202

cur_matrix_regs.masks.csc_c12 = dpp->tf_mask->CUR0_MATRIX_C12_A;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

213

dpp->base.ctx,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

223

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

43

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

46

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

50

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

92

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

95

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1012

dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1027

dpp, scl_data->taps.v_taps,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1034

dpp, scl_data->taps.h_taps,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1052

void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1056

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1072

if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1079

(dpp->scl_data.dscl_prog_data.sharpness_level

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1082

dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1083

dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1084

memcpy(dpp->scl_data.dscl_prog_data.isharp_delta, scl_data->dscl_prog_data.isharp_delta,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1087

if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1092

dpp->scl_data = *scl_data;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1094

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1120

dpp401_dscl_set_recout(dpp, rect);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1139

lb_config = dpp401_dscl_find_lb_memory_config(dpp, scl_data);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1140

dpp401_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1143

if (dpp->base.ctx->dc->config.prefer_easf)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

116

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1163

dpp401_dscl_set_manual_ratio_init(dpp, scl_data);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1181

dpp401_dscl_set_scl_filter(dpp, scl_data, ycbcr, bs_coeffs_updated);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1183

if (dpp->base.ctx->dc->config.prefer_easf)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

150

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

153

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

155

if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

160

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

161

dpp->base.ctx->dc->optimized_required = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

162

dpp->base.deferred_reg_writes.bits.disable_dscl = true;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

172

struct dcn401_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

179

if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

199

if (dpp->base.caps->max_lb_partitions == 31)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

233

struct dcn401_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

271

struct dcn401_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

288

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

329

filter_updated = (filter_h && (filter_h != dpp->filter_h))

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

330

|| (filter_v && (filter_v != dpp->filter_v));

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

333

filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

334

|| (filter_v_c && (filter_v_c != dpp->filter_v_c));

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

342

dpp, scl_data->taps.h_taps,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

345

dpp->filter_h = filter_h;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

348

dpp, scl_data->taps.v_taps,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

351

dpp->filter_v = filter_v;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

355

dpp, scl_data->taps.h_taps_c,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

360

dpp, scl_data->taps.v_taps_c,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

364

dpp->filter_h_c = filter_h_c;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

365

dpp->filter_v_c = filter_v_c;

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

368

scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

369

dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

44

dpp->tf_regs->reg

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

465

static enum lb_memory_config dpp401_dscl_find_lb_memory_config(struct dcn401_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

47

dpp->base.ctx

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

474

if (dpp->base.ctx->dc->debug.use_max_lb) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

481

dpp->base.caps->dscl_calc_lb_num_partitions(

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

488

dpp->base.caps->dscl_calc_lb_num_partitions(

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

497

dpp->base.caps->dscl_calc_lb_num_partitions(

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

505

dpp->base.caps->dscl_calc_lb_num_partitions(

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

51

dpp->tf_shift->field_name, dpp->tf_mask->field_name

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

517

struct dcn401_dpp *dpp, const struct scaler_data *data)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

521

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

634

static void dpp401_dscl_set_recout(struct dcn401_dpp *dpp,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

658

static void dpp401_dscl_program_easf_v(struct dpp *dpp_base, const struct scaler_data *scl_data)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

660

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

773

static void dpp401_dscl_program_easf_h(struct dpp *dpp_base, const struct scaler_data *scl_data)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

775

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

878

static void dpp401_dscl_program_easf(struct dpp *dpp_base, const struct scaler_data *scl_data)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

880

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

907

static void dpp401_dscl_disable_easf(struct dpp *dpp_base, const struct scaler_data *scl_data)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

909

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

921

struct dcn401_dpp *dpp, const uint32_t *filter)

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

950

static void dpp401_dscl_program_isharp(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

955

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1446

int dpp_id = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1488

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1499

hws->funcs.dpp_pg_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1505

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1514

hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1524

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1531

dpp->funcs->dpp_dppclk_control(dpp, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1542

pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1642

struct dpp *dpp = dc->res_pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1667

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1673

pipe_ctx->plane_res.dpp = dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1674

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1675

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2034

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2112

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2117

if (dpp == NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2120

dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2124

dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2131

&dpp->regamma_params, false)) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2132

dpp->funcs->dpp_program_regamma_pwl(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2133

dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2134

&dpp->regamma_params, OPP_REGAMMA_USER);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2136

dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2141

dpp->regamma_params.hw_points_num);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2790

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2820

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2833

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2849

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2853

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2854

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2858

static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2863

dpp->funcs->dpp_setup(dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2872

if (dpp->funcs->dpp_program_bias_and_scale)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2873

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2973

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2974

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2984

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3029

dpp->funcs->dpp_dppclk_control(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3030

dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3037

dpp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3068

dcn10_update_dpp(dpp, plane_state);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3197

pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3198

pipe_ctx->plane_res.dpp, hw_mult);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3647

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3860

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3869

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3870

pipe_ctx->plane_res.dpp, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3881

if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3896

pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3897

pipe_ctx->plane_res.dpp, &opt_attr);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

463

struct dpp *dpp = pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

466

dpp->funcs->dpp_read_state(dpp, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

467

if (dpp->funcs->dpp_get_gamut_remap) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

468

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

476

dpp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

522

dc->caps.color.dpp.input_lut_shared,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

523

dc->caps.color.dpp.icsc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

524

dc->caps.color.dpp.dgam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

525

dc->caps.color.dpp.dgam_rom_caps.srgb,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

526

dc->caps.color.dpp.dgam_rom_caps.bt2020,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

527

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

528

dc->caps.color.dpp.dgam_rom_caps.pq,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

529

dc->caps.color.dpp.dgam_rom_caps.hlg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

530

dc->caps.color.dpp.post_csc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

531

dc->caps.color.dpp.gamma_corr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

532

dc->caps.color.dpp.dgam_rom_for_yuv,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

533

dc->caps.color.dpp.hw_3d_lut,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

534

dc->caps.color.dpp.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

535

dc->caps.color.dpp.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

199

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

102

dpp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1072

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1092

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1120

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1289

hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1298

hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

150

dc->caps.color.dpp.input_lut_shared,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

151

dc->caps.color.dpp.icsc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

152

dc->caps.color.dpp.dgam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

153

dc->caps.color.dpp.dgam_rom_caps.srgb,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

154

dc->caps.color.dpp.dgam_rom_caps.bt2020,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

155

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

156

dc->caps.color.dpp.dgam_rom_caps.pq,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

157

dc->caps.color.dpp.dgam_rom_caps.hlg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

158

dc->caps.color.dpp.post_csc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

159

dc->caps.color.dpp.gamma_corr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

160

dc->caps.color.dpp.dgam_rom_for_yuv,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1600

if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

161

dc->caps.color.dpp.hw_3d_lut,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

162

dc->caps.color.dpp.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

163

dc->caps.color.dpp.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1686

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1693

dpp->funcs->dpp_dppclk_control(dpp, false, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1696

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1747

dpp->funcs->dpp_setup(dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1754

if (dpp->funcs->set_cursor_matrix) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1755

dpp->funcs->set_cursor_matrix(dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1759

if (dpp->funcs->dpp_program_bias_and_scale) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1761

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1781

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1782

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3178

struct dpp *dpp = res_pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3180

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3198

struct dpp *dpp = dc->res_pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3204

pipe_ctx->plane_res.dpp = dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3205

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3206

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

620

struct dpp *dpp5 = hws->ctx->dc->res_pool->dpps[dpp_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

714

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

731

dpp->funcs->dpp_dppclk_control(dpp, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

736

pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

89

struct dpp *dpp = pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

92

dpp->funcs->dpp_read_state(dpp, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

93

if (dpp->funcs->dpp_get_gamut_remap) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

94

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

288

struct dpp *dpp = res_pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

290

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

308

struct dpp *dpp = res_pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

314

pipe_ctx->plane_res.dpp = dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

315

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

316

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

381

int dpp_id = pipe_ctx->plane_res.dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

564

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

565

pipe_ctx->plane_res.dpp, attributes);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

102

dpp->inst,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

157

dc->caps.color.dpp.input_lut_shared,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

158

dc->caps.color.dpp.icsc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

159

dc->caps.color.dpp.dgam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

160

dc->caps.color.dpp.dgam_rom_caps.srgb,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

161

dc->caps.color.dpp.dgam_rom_caps.bt2020,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

162

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

163

dc->caps.color.dpp.dgam_rom_caps.pq,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

164

dc->caps.color.dpp.dgam_rom_caps.hlg,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

165

dc->caps.color.dpp.post_csc,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

166

dc->caps.color.dpp.gamma_corr,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

167

dc->caps.color.dpp.dgam_rom_for_yuv,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

168

dc->caps.color.dpp.hw_3d_lut,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

169

dc->caps.color.dpp.ogam_ram,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

170

dc->caps.color.dpp.ocsc);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

234

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

256

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

318

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

373

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

88

struct dpp *dpp = pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

91

dpp->funcs->dpp_read_state(dpp, &s);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

93

if (dpp->funcs->dpp_get_gamut_remap) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

94

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

457

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

556

struct dpp *dpp = hws->ctx->dc->res_pool->dpps[dpp_inst];

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

557

if (dpp && dpp->funcs->dpp_force_disable_cursor)

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

558

dpp->funcs->dpp_force_disable_cursor(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

442

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

479

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

528

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1050

if (j == PG_DPP && new_pipe->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1051

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1053

if (j == PG_MPCC && new_pipe->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1078

cur_pipe->plane_res.dpp != new_pipe->plane_res.dpp &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1079

new_pipe->plane_res.dpp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1080

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

482

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

694

struct dpp *dpp = dc->res_pool->dpps[i];

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

719

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

725

pipe_ctx->plane_res.dpp = dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

726

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

727

hubp->mpcc_id = dpp->inst;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

818

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

828

dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

829

dpp->funcs->dpp_dppclk_control(dpp, false, true);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

861

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

880

dpp->funcs->dpp_dppclk_control(dpp, false, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

881

dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

886

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

958

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

961

if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1077

struct dpp *dpp = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1222

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2569

if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2650

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2666

hws->funcs.dpp_pg_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2672

dpp->funcs->dpp_reset(dpp);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2682

hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

410

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

614

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

110

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h

44

struct dpp;

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

113

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer_private.h

67

struct dpp;

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

248

struct dpp *dpps[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

381

struct dpp *dpp;

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

214

struct dpp *dpp_base, const struct pwl_params *params);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

216

void (*dpp_set_pre_degam)(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

219

void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

223

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

226

void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

228

void (*dpp_reset)(struct dpp *dpp);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

230

void (*dpp_set_scaler)(struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

234

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

239

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

244

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

248

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

252

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

256

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

260

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

265

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

269

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

273

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

277

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

282

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

286

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

290

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

293

void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

297

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

304

void (*dpp_full_bypass)(struct dpp *dpp_base);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

307

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

311

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

319

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

323

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

327

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

332

struct dpp *dpp);

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

334

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

337

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

340

struct dpp *dpp,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

343

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

346

void (*dpp_get_gamut_remap)(struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

349

struct dpp *dpp_base,

sys/dev/pci/drm/amd/display/dc/inc/hw/dpp.h

353

void (*dpp_force_disable_cursor)(struct dpp *dpp_base);

sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h

231

int dpp[MAX_PIPES];

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1104

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1365

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1366

dc->caps.color.dpp.input_lut_shared = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1367

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1368

dc->caps.color.dpp.dgam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1369

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1370

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1371

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1372

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1373

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1374

dc->caps.color.dpp.post_csc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1375

dc->caps.color.dpp.gamma_corr = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1376

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1378

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1379

dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1380

dc->caps.color.dpp.ogam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1381

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1382

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1383

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1384

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1385

dc->caps.color.dpp.ocsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

563

static void dcn10_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

565

kfree(TO_DCN10_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

566

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

569

static struct dpp *dcn10_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

573

struct dcn10_dpp *dpp =

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

576

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

579

dpp1_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

581

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1494

next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1550

secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2166

sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2440

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2441

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2442

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2443

dc->caps.color.dpp.dgam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2444

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2445

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2446

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2447

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2448

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2449

dc->caps.color.dpp.post_csc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2450

dc->caps.color.dpp.gamma_corr = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2451

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2453

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2454

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2456

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2457

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2458

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2459

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2460

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2461

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

725

void dcn20_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

727

kfree(TO_DCN20_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

728

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

731

struct dpp *dcn20_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

735

struct dcn20_dpp *dpp =

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

738

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

741

if (dpp2_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

743

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

746

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

80

void dcn20_dpp_destroy(struct dpp **dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

82

struct dpp *dcn20_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1023

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1121

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1122

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1123

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1124

dc->caps.color.dpp.dgam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1125

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1126

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1127

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1128

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1129

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1130

dc->caps.color.dpp.post_csc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1131

dc->caps.color.dpp.gamma_corr = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1132

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1134

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1135

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1137

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1138

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1139

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1140

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1141

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1142

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

621

static void dcn201_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

623

kfree(TO_DCN201_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

624

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

627

static struct dpp *dcn201_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

631

struct dcn201_dpp *dpp =

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

634

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

637

if (dpp201_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

639

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

641

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1426

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1427

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1428

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1429

dc->caps.color.dpp.dgam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1430

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1431

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1432

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1433

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1434

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1435

dc->caps.color.dpp.post_csc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1436

dc->caps.color.dpp.gamma_corr = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1437

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1439

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1440

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1442

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1443

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1444

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1445

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1446

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1447

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

499

static struct dpp *dcn21_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

503

struct dcn20_dpp *dpp =

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

506

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

509

if (dpp2_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

511

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

514

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1537

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2321

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2322

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2323

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2324

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2325

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2326

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2327

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2328

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2329

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2330

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2331

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2332

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2334

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2335

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2337

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2338

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2339

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2340

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2341

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2342

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

742

static void dcn30_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

744

kfree(TO_DCN20_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

745

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

748

static struct dpp *dcn30_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

752

struct dcn3_dpp *dpp =

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

755

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

758

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

760

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

763

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1450

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1451

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1452

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1453

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1454

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1455

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1456

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1457

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1458

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1459

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1460

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1461

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1463

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1464

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1466

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1467

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1468

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1469

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1470

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1471

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

708

static void dcn301_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

710

kfree(TO_DCN20_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

711

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

714

static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

716

struct dcn3_dpp *dpp =

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

719

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

722

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

724

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

727

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1241

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1242

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1243

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1244

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1245

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1246

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1247

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1248

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1249

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1250

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1251

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1252

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1254

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1255

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1257

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1258

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1259

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1260

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1261

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1262

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

538

static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

540

struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

542

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

545

if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

546

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

549

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1185

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1186

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1187

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1188

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1189

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1190

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1191

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1192

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1193

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1194

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1195

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1196

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1198

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1199

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1201

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1202

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1203

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1204

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1205

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1206

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

516

static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

518

struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

520

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

523

if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

524

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

527

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1926

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1927

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1928

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1929

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1930

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1931

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1932

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1933

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1934

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1935

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1936

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1937

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1939

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1940

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1942

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1943

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1944

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1945

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1946

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1947

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

908

static void dcn31_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

910

kfree(TO_DCN20_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

911

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

914

static struct dpp *dcn31_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

918

struct dcn3_dpp *dpp =

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

921

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

924

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

926

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

929

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1857

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1858

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1859

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1860

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1861

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1862

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1863

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1864

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1865

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1866

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1867

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1868

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1870

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1871

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1873

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1874

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1875

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1876

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1877

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1878

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

913

.dpp = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

944

static void dcn31_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

946

kfree(TO_DCN20_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

947

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

950

static struct dpp *dcn31_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

954

struct dcn3_dpp *dpp =

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

957

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

960

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

962

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

965

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1894

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1895

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1896

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1897

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1898

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1899

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1900

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1901

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1902

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1903

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1904

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1905

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1907

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1908

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1910

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1911

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1912

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1913

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1914

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1915

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

906

static void dcn31_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

908

kfree(TO_DCN20_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

909

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

912

static struct dpp *dcn31_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

916

struct dcn3_dpp *dpp =

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

919

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

922

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

924

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

927

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1770

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1771

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1772

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1773

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1774

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1775

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1776

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1777

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1778

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1779

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1780

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1781

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1783

dc->caps.color.dpp.hw_3d_lut = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1784

dc->caps.color.dpp.ogam_ram = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1786

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1787

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1788

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1789

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1790

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1791

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

900

static void dcn31_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

902

kfree(TO_DCN20_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

903

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

906

static struct dpp *dcn31_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

910

struct dcn3_dpp *dpp =

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

913

if (!dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

916

if (dpp3_construct(dpp, ctx, inst,

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

918

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

921

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2245

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2246

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2247

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2248

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2249

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2250

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2251

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2252

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2253

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2254

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2255

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2256

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2258

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2259

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2261

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2262

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2263

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2264

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2265

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2266

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2765

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2824

free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2857

free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

914

static void dcn32_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

916

kfree(TO_DCN30_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

917

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

920

static struct dpp *dcn32_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1745

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1746

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1747

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1748

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1749

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1750

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1751

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1752

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1753

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1754

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1755

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1756

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1758

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1759

dc->caps.color.dpp.ogam_ram = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1761

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1762

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1763

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1764

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1765

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1766

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

908

static void dcn321_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

910

kfree(TO_DCN30_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

911

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

914

static struct dpp *dcn321_dpp_create(

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1880

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1881

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1882

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1883

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1884

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1885

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1886

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1887

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1888

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1889

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1890

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1891

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1893

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1894

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1896

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1897

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1898

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1899

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1900

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1901

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

752

.dpp = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

802

static void dcn35_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

804

kfree(TO_DCN20_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

805

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

808

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

810

struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

811

bool success = (dpp != NULL);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

823

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

827

dpp,

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

828

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

829

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

833

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1853

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1854

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1855

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1856

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1857

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1858

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1859

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1860

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1861

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1862

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1863

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1864

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1866

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1867

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1869

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1870

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1871

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1872

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1873

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1874

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

732

.dpp = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

782

static void dcn35_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

784

kfree(TO_DCN20_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

785

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

788

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

790

struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

791

bool success = (dpp != NULL);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

803

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

807

dpp,

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

808

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

809

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

813

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1853

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1854

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1855

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1856

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1857

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1858

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1859

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1860

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1861

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1862

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1863

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1864

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1866

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1867

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1869

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1870

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1871

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1872

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1873

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1874

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

733

.dpp = true,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

783

static void dcn35_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

785

kfree(TO_DCN20_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

786

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

789

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

791

struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

792

bool success = (dpp != NULL);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

804

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

808

dpp,

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

809

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

810

return &dpp->base;

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

814

kfree(dpp);

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1923

dc->caps.color.dpp.dcn_arch = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1924

dc->caps.color.dpp.input_lut_shared = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1925

dc->caps.color.dpp.icsc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1926

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1927

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1928

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1929

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1930

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1931

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1932

dc->caps.color.dpp.post_csc = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1933

dc->caps.color.dpp.gamma_corr = 1;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1934

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1936

dc->caps.color.dpp.hw_3d_lut = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1937

dc->caps.color.dpp.ogam_ram = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1939

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1940

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1941

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1942

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1943

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1944

dc->caps.color.dpp.ocsc = 0;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

907

static void dcn401_dpp_destroy(struct dpp **dpp)

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

909

kfree(TO_DCN401_DPP(*dpp));

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

910

*dpp = NULL;

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

913

static struct dpp *dcn401_dpp_create(

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1697

dc_caps->dpp.dcn_arch == 1) {

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1700

dc_caps->dpp.dgam_rom_caps.pq == 1)

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1704

dc_caps->dpp.dgam_rom_caps.gamma2_2 == 1)

sys/dev/pci/drm/amd/display/modules/color/color_gamma.c

1709

dc_caps->dpp.dgam_rom_caps.hlg == 1)

usr.bin/ssh/sshbuf.c

370

sshbuf_reserve(struct sshbuf *buf, size_t len, u_char **dpp)

usr.bin/ssh/sshbuf.c

375

if (dpp != NULL)

usr.bin/ssh/sshbuf.c

376

*dpp = NULL;

usr.bin/ssh/sshbuf.c

384

if (dpp != NULL)

usr.bin/ssh/sshbuf.c

385

*dpp = dp;

usr.bin/ssh/sshbuf.h

139

int sshbuf_reserve(struct sshbuf *buf, size_t len, u_char **dpp);

usr.bin/tftp/tftpsubs.c

109

readit(FILE *file, struct tftphdr **dpp, int convert, int segment_size)

usr.bin/tftp/tftpsubs.c

120

*dpp = (struct tftphdr *)b->buf; /* set caller's ptr */

usr.bin/tftp/tftpsubs.c

179

writeit(FILE *file, struct tftphdr **dpp, int ct, int convert)

usr.bin/tftp/tftpsubs.c

187

*dpp = (struct tftphdr *)bfs[current].buf;