sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1254

struct dmub_srv *dmub_srv = adev->dm.dmub_srv;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1266

if (!dmub_srv)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1282

if (dmub_srv->hw_funcs.init_reg_offsets)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1283

dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1285

status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12893

if (adev->dm.dmub_srv)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1297

status = dmub_srv_hw_reset(dmub_srv);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13157

if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13189

if (ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13190

ctx->dmub_srv->reg_helper_offload.gather_in_progress &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13191

!ctx->dmub_srv->reg_helper_offload.should_burst_write) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13364

return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13369

return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1388

status = dmub_srv_hw_init(dmub_srv, &hw_params);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1395

status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1405

if (!adev->dm.dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1406

adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1407

if (!adev->dm.dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1443

struct dmub_srv *dmub_srv = adev->dm.dmub_srv;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1448

if (!dmub_srv) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1453

status = dmub_srv_is_hw_init(dmub_srv, &init);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1459

status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2273

dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2452

struct dmub_srv *dmub_srv;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2537

adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2538

dmub_srv = adev->dm.dmub_srv;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2540

if (!dmub_srv) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2552

status = dmub_srv_create(dmub_srv, &create_params);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2575

status = dmub_srv_calc_region_info(dmub_srv, &region_params,

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2613

status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2665

if (adev->dm.dmub_srv) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2666

dmub_srv_destroy(adev->dm.dmub_srv);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2667

kfree(adev->dm.dmub_srv);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2668

adev->dm.dmub_srv = NULL;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2745

} else if (adev->dm.dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3240

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3424

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3457

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3516

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3929

if (dc->caps.ips_support && dc->ctx->dmub_srv->idle_allowed) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4733

if (dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5113

if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

351

struct dmub_srv *dmub_srv;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.h

86

struct dmub_srv;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1029

if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1031

(bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2687

dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3247

struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3291

struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

919

if (adev->dm.dmub_srv)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

920

fw_meta_info = &adev->dm.dmub_srv->meta_info;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

98

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub ||

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

99

!dc->ctx->dmub_srv->dmub->feature_caps.replay_supported)

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

1059

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

1061

enable_lvtma_control_dmcub(bp->base.ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

180

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

182

encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

196

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

296

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

298

transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

378

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

406

transmitter_control_dmcub_v1_7(bp->base.ctx->dmub_srv, &dig_v1_7);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

425

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

553

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

555

set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

569

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

862

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

864

enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/bios/command_table2.c

880

if (bp->base.ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/core/dc.c

1289

memcpy(color, &dc->ctx->dmub_srv->dmub->visual_confirm_color, sizeof(struct tg_color));

sys/dev/pci/drm/amd/display/dc/core/dc.c

1566

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

sys/dev/pci/drm/amd/display/dc/core/dc.c

2304

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);

sys/dev/pci/drm/amd/display/dc/core/dc.c

4159

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4429

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/core/dc.c

4499

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, current_stream_mask);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5453

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5464

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);

sys/dev/pci/drm/amd/display/dc/core/dc.c

547

dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/core/dc.c

5473

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);

sys/dev/pci/drm/amd/display/dc/core/dc.c

5648

if (!dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/core/dc.c

5651

return dc->ctx->dmub_srv->idle_allowed;

sys/dev/pci/drm/amd/display/dc/core/dc.c

567

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

sys/dev/pci/drm/amd/display/dc/core/dc.c

585

struct dc_dmub_srv *dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc.c

5867

dmub_enable_outbox_notification(dc_ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/core/dc.c

605

dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc.c

608

if (dmub_srv)

sys/dev/pci/drm/amd/display/dc/core/dc.c

609

dc_stream_forward_dmub_crc_window(dmub_srv, rect, &mux_mapping, is_stop);

sys/dev/pci/drm/amd/display/dc/core/dc.c

6103

dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/core/dc.c

620

dc_stream_forward_dmub_multiple_crc_window(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/core/dc.c

644

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

sys/dev/pci/drm/amd/display/dc/core/dc.c

651

struct dc_dmub_srv *dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc.c

670

dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc.c

673

if (dmub_srv)

sys/dev/pci/drm/amd/display/dc/core/dc.c

674

dc_stream_forward_dmub_multiple_crc_window(dmub_srv, window, &mux_mapping, stop);

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

638

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

711

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c

802

block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/core/dc_stat.c

55

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/core/dc_stat.c

85

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

254

if (dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

391

if (dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

100

struct dmub_srv *dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

113

struct dmub_srv *dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1141

bool dc_dmub_check_min_version(struct dmub_srv *srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1150

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1231

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1234

dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1260

dc_dmub_srv_wait_for_idle(dc->ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

127

struct dmub_srv *dmub = dc_dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1352

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1355

dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

143

struct dmub_srv *dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1439

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1447

dmub_srv_sync_inboxes(dc->ctx->dmub_srv->dmub);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1470

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1483

struct dmub_srv *dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1554

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1611

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1644

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1671

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1761

struct dmub_fams2_config_v2 *config = (struct dmub_fams2_config_v2 *)dc->ctx->dmub_srv->dmub->ib_mem_gart.cpu_addr;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1771

cmd.ib_fams2_config.ib_data.src.quad_part = dc->ctx->dmub_srv->dmub->ib_mem_gart.gpu_addr;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

185

struct dmub_srv *dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1966

dmub_flush_buffer_mem(&ctx->dmub_srv->dmub->scratch_mem_fb);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1973

cmd.ips_query_residency_info.info_data.dest.quad_part = ctx->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

1983

memcpy(driver_info, ctx->dmub_srv->dmub->scratch_mem_fb.cpu_addr, bytes);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2002

lsdma_data->u.init_data.gpu_addr_base.quad_part = dc_ctx->dmub_srv->dmub->lsdma_rb_fb.gpu_addr;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2003

lsdma_data->u.init_data.ring_size = dc_ctx->dmub_srv->dmub->lsdma_rb_fb.size;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

2236

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

263

struct dmub_srv *dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

313

struct dmub_srv *dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

345

struct dmub_srv *dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

367

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

45

struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

51

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

552

memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

66

void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

68

if (*dmub_srv) {

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

69

kfree(*dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

70

*dmub_srv = NULL;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c

76

struct dmub_srv *dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

103

bool dc_dmub_check_min_version(struct dmub_srv *srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

32

struct dmub_srv;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

49

struct dmub_srv *dmub;

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

93

void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

94

void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);

sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.h

95

void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);

sys/dev/pci/drm/amd/display/dc/dc_helper.c

146

struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

171

struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

210

struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

237

if (ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/dc_helper.c

238

ctx->dmub_srv->reg_helper_offload.gather_in_progress)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

267

if (ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/dc_helper.c

268

ctx->dmub_srv->reg_helper_offload.gather_in_progress) {

sys/dev/pci/drm/amd/display/dc/dc_helper.c

436

if (ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/dc_helper.c

437

ctx->dmub_srv->reg_helper_offload.gather_in_progress) {

sys/dev/pci/drm/amd/display/dc/dc_helper.c

494

if (ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/dc_helper.c

495

ctx->dmub_srv->reg_helper_offload.gather_in_progress) {

sys/dev/pci/drm/amd/display/dc/dc_helper.c

633

if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) {

sys/dev/pci/drm/amd/display/dc/dc_helper.c

635

&ctx->dmub_srv->reg_helper_offload;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

648

if (!ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

651

offload = &ctx->dmub_srv->reg_helper_offload;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

677

if (!ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/dc_helper.c

680

offload = &ctx->dmub_srv->reg_helper_offload;

sys/dev/pci/drm/amd/display/dc/dc_helper.c

685

dc_dmub_srv_wait_for_idle(ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);

sys/dev/pci/drm/amd/display/dc/dc_types.h

817

struct dc_dmub_srv *dmub_srv;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

169

dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

172

memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)src, bytes);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

178

cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

229

dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

232

memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)pData, bytes);

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

238

cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

sys/dev/pci/drm/amd/display/dc/dce/dmub_abm_lcd.c

249

memcpy((void *)pData, dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, bytes);

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

31

void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

50

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

53

void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

59

dc_dmub_srv_clear_inbox0_ack(dmub_srv);

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

60

dc_dmub_srv_send_inbox0_cmd(dmub_srv, data);

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

61

dc_dmub_srv_wait_for_inbox0_ack(dmub_srv);

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

67

if (!link->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

32

void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

37

void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,

sys/dev/pci/drm/amd/display/dc/dce/dmub_outbox.c

39

void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv)

sys/dev/pci/drm/amd/display/dc/dce/dmub_outbox.c

51

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dce/dmub_outbox.h

31

void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv);

sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c

199

dc_wake_and_execute_dmub_cmd(dc->dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

44

struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

71

struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

105

struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/dm_services.h

127

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dc/dm_services.h

128

void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);

sys/dev/pci/drm/amd/display/dc/dm_services.h

41

struct dmub_srv;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1029

if (ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

874

if (ctx->dc->ctx->dmub_srv &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1787

if (!dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv))

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2255

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1470

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1862

params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

825

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

826

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

827

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

918

if (!dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

276

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

277

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

278

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

438

if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

261

if (!dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

350

if (!dc->ctx || !dc->ctx->dmub_srv)

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

417

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

435

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

986

if (dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

987

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

988

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

989

dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

990

dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

991

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

992

dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

995

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

999

} else if (dc->ctx->dmub_srv->dmub->fw_version <

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

267

if (dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

313

if (dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

314

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

315

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

316

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

317

dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1279

if (!dc->ctx->dmub_srv || !dc->current_state)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1485

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1492

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1507

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1515

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1637

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1659

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

355

if (dc->ctx->dmub_srv) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

356

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

357

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

358

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0;

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

359

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

887

dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

935

dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1485

if (!link->ctx->dmub_srv ||

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

117

struct dc_dmub_srv *dmub_srv = link->ctx->dmub_srv;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_dpia.c

126

if (dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

1002

void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

1015

enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

1025

void dmub_srv_cmd_get_response(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

1038

enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

1055

enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

1069

enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

406

void (*init)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

408

void (*reset)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

410

void (*reset_release)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

412

void (*backdoor_load)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

416

void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

419

void (*setup_windows)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

427

void (*setup_mailbox)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

430

uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

432

uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

434

void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

436

void (*setup_out_mailbox)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

439

uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

441

void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

443

void (*setup_outbox0)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

446

uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

448

void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

450

uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

452

uint32_t (*emul_get_inbox1_wptr)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

454

void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

456

bool (*is_supported)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

458

bool (*is_psrsu_supported)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

460

bool (*is_hw_init)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

461

bool (*is_hw_powered_up)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

463

void (*enable_dmub_boot_options)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

466

void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

468

union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

470

union dmub_fw_boot_options (*get_fw_boot_option)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

472

void (*set_gpint)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

475

bool (*is_gpint_acked)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

478

uint32_t (*get_gpint_response)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

480

uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

482

void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

483

void (*clear_inbox0_ack_register)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

484

uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

485

void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

486

uint32_t (*get_current_time)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

488

void (*get_diagnostic_data)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

490

bool (*should_detect)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

491

void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

493

void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

495

void (*send_reg_inbox0_cmd_msg)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

497

uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

498

void (*read_reg_inbox0_cmd_rsp)(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

500

void (*write_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

501

void (*clear_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

502

void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

504

uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

505

void (*write_reg_outbox0_rdy_int_ack)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

506

void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

507

void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

508

uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

509

void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

630

enum dmub_status dmub_srv_create(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

637

void dmub_srv_destroy(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

653

dmub_srv_calc_region_info(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

670

enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

687

enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

697

enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

712

enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

728

enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

743

enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

756

enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

76

struct dmub_srv;

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

771

enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

774

bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

792

enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

811

enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

828

enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

845

enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

867

dmub_srv_send_gpint_command(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

884

enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

900

enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

923

enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

926

enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

929

enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

932

bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

934

bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

936

bool dmub_srv_should_detect(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

949

enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

963

enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

975

enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/dmub_srv.h

990

void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

sys/dev/pci/drm/amd/display/dmub/dmub_srv_stat.h

38

enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

146

void dmub_dcn20_reset_release(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

154

void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

189

void dmub_dcn20_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

274

void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

286

uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

291

uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

296

void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

301

void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

313

uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

322

void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

331

void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

339

uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

344

void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

349

bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

358

bool dmub_dcn20_is_supported(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

367

void dmub_dcn20_set_gpint(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

373

bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

384

uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

389

union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

397

void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

404

void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

412

uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

417

void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

60

static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

87

bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.c

94

void dmub_dcn20_reset(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

185

void dmub_dcn20_init(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

187

void dmub_dcn20_reset(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

189

void dmub_dcn20_reset_release(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

191

void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

195

void dmub_dcn20_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

203

void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

206

uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

208

uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

210

void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

212

void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

215

uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

217

void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

219

void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

222

uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

224

void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

226

bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

228

bool dmub_dcn20_is_supported(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

230

void dmub_dcn20_set_gpint(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

233

bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

236

uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

238

void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

240

void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

242

union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

244

bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

246

bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

248

uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

250

void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h

31

struct dmub_srv;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c

122

void dmub_dcn30_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c

60

static void dmub_dcn30_get_fb_base_offset(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.c

87

void dmub_dcn30_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.h

37

void dmub_dcn30_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn30.h

41

void dmub_dcn30_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

149

void dmub_dcn31_reset_release(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

157

void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

190

void dmub_dcn31_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

244

void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

251

uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

256

uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

261

void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

266

void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

273

uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

282

void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

291

bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

302

bool dmub_dcn31_is_supported(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

311

bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

316

void dmub_dcn31_set_gpint(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

322

bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

333

uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

338

uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

353

union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

361

union dmub_fw_boot_options dmub_dcn31_get_fw_boot_option(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

369

void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

387

void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

395

void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

403

uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

408

void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

413

uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

418

void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

489

bool dmub_dcn31_should_detect(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

56

static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.c

83

void dmub_dcn31_reset(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

187

void dmub_dcn31_init(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

189

void dmub_dcn31_reset(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

191

void dmub_dcn31_reset_release(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

193

void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

197

void dmub_dcn31_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

205

void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

208

uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

210

uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

212

void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

214

void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

217

uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

219

void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

221

bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

223

bool dmub_dcn31_is_supported(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

225

bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

227

void dmub_dcn31_set_gpint(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

230

bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

233

uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

235

uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

237

void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

239

void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

241

union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

243

union dmub_fw_boot_options dmub_dcn31_get_fw_boot_option(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

245

void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

248

uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

250

void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

252

uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

254

void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

256

bool dmub_dcn31_should_detect(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h

31

struct dmub_srv;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn314.c

64

bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn314.h

33

bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

149

void dmub_dcn32_reset_release(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

157

void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

190

void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

220

void dmub_dcn32_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

274

void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

281

uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

286

uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

291

void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

296

void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

303

uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

312

void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

321

bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

332

bool dmub_dcn32_is_supported(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

341

void dmub_dcn32_set_gpint(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

347

bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

358

uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

363

uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

378

union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

386

void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

395

void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

40

void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

403

void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

411

uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

416

void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

421

uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

426

void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

493

void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

506

void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

511

void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

516

uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

521

void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

62

static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.c

89

void dmub_dcn32_reset(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

198

void dmub_dcn32_reset(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

200

void dmub_dcn32_reset_release(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

202

void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

206

void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

210

void dmub_dcn32_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

218

void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

221

uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

223

uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

225

void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

227

void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

230

uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

232

void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

234

bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

236

bool dmub_dcn32_is_supported(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

238

void dmub_dcn32_set_gpint(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

241

bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

244

uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

246

uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

248

void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

250

void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

252

union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

254

void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

257

uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

259

void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

261

uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

263

void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

265

void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

266

void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

267

void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

268

uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

269

void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

271

void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h

31

struct dmub_srv;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

148

void dmub_dcn35_reset_release(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

162

void dmub_dcn35_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

193

void dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

217

void dmub_dcn35_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

280

void dmub_dcn35_setup_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

287

uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

292

uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

297

void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

302

void dmub_dcn35_setup_out_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

309

uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

318

void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

327

bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

338

bool dmub_dcn35_is_supported(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

347

void dmub_dcn35_set_gpint(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

353

bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

364

uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

369

uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

384

union dmub_fw_boot_status dmub_dcn35_get_fw_boot_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

392

union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

40

void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) {

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

400

void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

425

void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

433

void dmub_dcn35_setup_outbox0(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

441

uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

446

void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

451

uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

456

void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

523

void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

536

bool dmub_dcn35_should_detect(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

543

void dmub_dcn35_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

548

void dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

553

uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

558

bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

59

static void dmub_dcn35_get_fb_base_offset(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.c

88

void dmub_dcn35_reset(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

203

void dmub_dcn35_init(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

205

void dmub_dcn35_reset(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

207

void dmub_dcn35_reset_release(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

209

void dmub_dcn35_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

213

void dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

217

void dmub_dcn35_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

225

void dmub_dcn35_setup_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

228

uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

230

uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

232

void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

234

void dmub_dcn35_setup_out_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

237

uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

239

void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

241

bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

243

bool dmub_dcn35_is_supported(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

245

void dmub_dcn35_set_gpint(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

248

bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

251

uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

253

uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

255

void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

257

void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

259

union dmub_fw_boot_status dmub_dcn35_get_fw_boot_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

261

union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

263

void dmub_dcn35_setup_outbox0(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

266

uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

268

void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

270

uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

272

void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

274

void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

276

void dmub_dcn35_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

278

void dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

280

uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

282

bool dmub_dcn35_should_detect(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

284

bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

286

void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h

31

struct dmub_srv;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn351.c

16

void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn351.h

11

void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn351.h

9

struct dmub_srv;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn36.c

16

void dmub_srv_dcn36_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn36.h

11

void dmub_srv_dcn36_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn36.h

9

struct dmub_srv;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

118

void dmub_dcn401_reset_release(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

126

void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

163

void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

197

void dmub_dcn401_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

260

void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

267

uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

272

uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

277

void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

282

void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

289

uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

298

void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

307

bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

318

bool dmub_dcn401_is_supported(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

327

void dmub_dcn401_set_gpint(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

333

bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

344

uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

349

uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

36

static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

364

union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

372

void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

383

void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

391

void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

399

uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

404

void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

409

uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

414

void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

487

void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

500

void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

505

void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

510

uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

515

void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

584

uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

592

void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

617

void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

622

void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

627

void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

63

void dmub_dcn401_reset(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

632

void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

638

void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

643

void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

648

uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

656

void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.c

661

uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

10

struct dmub_srv;

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

202

void dmub_dcn401_reset(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

204

void dmub_dcn401_reset_release(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

206

void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

210

void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

214

void dmub_dcn401_setup_windows(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

222

void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

225

uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

227

uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

229

void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

231

void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

234

uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

236

void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

238

bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

240

bool dmub_dcn401_is_supported(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

242

void dmub_dcn401_set_gpint(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

245

bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

248

uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

250

uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

252

void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

254

void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

256

union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

258

void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

261

uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

263

void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

265

uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

267

void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

269

void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

270

void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

271

void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

272

uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

274

void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

276

uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

277

void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

279

void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

280

void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

281

void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

283

void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

284

void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

285

void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *msg);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

286

uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

287

void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);

sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h

288

uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub);

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

104

void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

72

void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.c

89

void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

114

void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

117

void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

120

void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

31

struct dmub_srv;

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1017

dmub_srv_send_gpint_command(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1049

enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1065

enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1081

enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1095

enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1109

enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1144

bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1151

bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1159

bool dmub_srv_should_detect(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1167

enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1176

enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1193

enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1203

void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1212

void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1220

enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1255

void dmub_srv_cmd_get_response(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1268

static enum dmub_status dmub_srv_sync_reg_inbox0(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1279

static enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1300

enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1315

enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

1342

enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

162

static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

445

enum dmub_status dmub_srv_create(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

496

void dmub_srv_destroy(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

522

dmub_srv_calc_region_info(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

581

enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

615

enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

629

enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

645

enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

805

enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

832

enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

854

enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

880

bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

891

enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

909

enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

933

static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub)

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

952

enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c

990

enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,

sys/dev/pci/drm/amd/display/dmub/src/dmub_srv_stat.c

46

enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,