sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10038

dml_uint_t state_idx)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10042

if (state_idx >= (dml_uint_t)states->num_states) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10053

dml_uint_t state_idx)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10092

dml_uint_t state_idx,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10124

dml_uint_t state_idx,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10133

for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; ++k)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10156

static dml_uint_t mode_support_pwr_states(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10157

dml_uint_t *lowest_state_idx,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10160

dml_uint_t start_state_idx,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10161

dml_uint_t end_state_idx)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10163

dml_uint_t state_idx = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10185

dml_uint_t dml_mode_support_ex(struct dml_mode_support_ex_params_st *in_out_params)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10187

dml_uint_t result;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

102

dml_uint_t *RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10201

dml_bool_t dml_get_is_phantom_pipe(struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10203

dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10208

#define dml_get_per_surface_var_func(variable, type, interval_var) type dml_get_##variable(struct display_mode_lib_st *mode_lib, dml_uint_t surface_idx) \

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10210

dml_uint_t plane_idx; \

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10250

dml_get_var_func(comp_buffer_size_kbytes, dml_uint_t, mode_lib->mp.CompressedBufferSizeInkByte);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10251

dml_get_var_func(pixel_chunk_size_in_kbyte, dml_uint_t, mode_lib->ms.ip.pixel_chunk_size_kbytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10252

dml_get_var_func(alpha_pixel_chunk_size_in_kbyte, dml_uint_t, mode_lib->ms.ip.alpha_pixel_chunk_size_kbytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10253

dml_get_var_func(meta_chunk_size_in_kbyte, dml_uint_t, mode_lib->ms.ip.meta_chunk_size_kbytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10254

dml_get_var_func(min_pixel_chunk_size_in_byte, dml_uint_t, mode_lib->ms.ip.min_pixel_chunk_size_bytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10255

dml_get_var_func(min_meta_chunk_size_in_byte, dml_uint_t, mode_lib->ms.ip.min_meta_chunk_size_bytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10256

dml_get_var_func(total_immediate_flip_bytes, dml_uint_t, mode_lib->mp.TotImmediateFlipBytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10258

dml_get_per_surface_var_func(dsc_delay, dml_uint_t, mode_lib->mp.DSCDelay); // this is the dsc latency

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10264

dml_get_per_surface_var_func(dst_x_after_scaler, dml_uint_t, mode_lib->mp.DSTXAfterScaler);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10265

dml_get_per_surface_var_func(dst_y_after_scaler, dml_uint_t, mode_lib->mp.DSTYAfterScaler);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10303

dml_get_per_surface_var_func(dpte_group_size_in_bytes, dml_uint_t, mode_lib->mp.dpte_group_bytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10304

dml_get_per_surface_var_func(vm_group_size_in_bytes, dml_uint_t, mode_lib->mp.vm_group_bytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10305

dml_get_per_surface_var_func(swath_height_l, dml_uint_t, mode_lib->ms.SwathHeightY);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10306

dml_get_per_surface_var_func(swath_height_c, dml_uint_t, mode_lib->ms.SwathHeightC);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10307

dml_get_per_surface_var_func(dpte_row_height_l, dml_uint_t, mode_lib->mp.dpte_row_height);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10308

dml_get_per_surface_var_func(dpte_row_height_c, dml_uint_t, mode_lib->mp.dpte_row_height_chroma);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10309

dml_get_per_surface_var_func(dpte_row_height_linear_l, dml_uint_t, mode_lib->mp.dpte_row_height_linear);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10310

dml_get_per_surface_var_func(dpte_row_height_linear_c, dml_uint_t, mode_lib->mp.dpte_row_height_linear_chroma);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10311

dml_get_per_surface_var_func(meta_row_height_l, dml_uint_t, mode_lib->mp.meta_row_height);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10312

dml_get_per_surface_var_func(meta_row_height_c, dml_uint_t, mode_lib->mp.meta_row_height_chroma);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10314

dml_get_per_surface_var_func(vstartup_calculated, dml_uint_t, mode_lib->mp.VStartup);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10315

dml_get_per_surface_var_func(vupdate_offset, dml_uint_t, mode_lib->mp.VUpdateOffsetPix);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10316

dml_get_per_surface_var_func(vupdate_width, dml_uint_t, mode_lib->mp.VUpdateWidthPix);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10317

dml_get_per_surface_var_func(vready_offset, dml_uint_t, mode_lib->mp.VReadyOffsetPix);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10318

dml_get_per_surface_var_func(vready_at_or_after_vsync, dml_uint_t, mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10319

dml_get_per_surface_var_func(min_dst_y_next_start, dml_uint_t, mode_lib->mp.MIN_DST_Y_NEXT_START);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10320

dml_get_per_surface_var_func(det_stored_buffer_size_l_bytes, dml_uint_t, mode_lib->ms.DETBufferSizeY);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10321

dml_get_per_surface_var_func(det_stored_buffer_size_c_bytes, dml_uint_t, mode_lib->ms.DETBufferSizeC);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10322

dml_get_per_surface_var_func(use_mall_for_static_screen, dml_uint_t, mode_lib->mp.UsesMALLForStaticScreen);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10323

dml_get_per_surface_var_func(surface_size_for_mall, dml_uint_t, mode_lib->mp.SurfaceSizeInTheMALL);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10324

dml_get_per_surface_var_func(dcc_max_uncompressed_block_l, dml_uint_t, mode_lib->mp.DCCYMaxUncompressedBlock);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10325

dml_get_per_surface_var_func(dcc_max_compressed_block_l, dml_uint_t, mode_lib->mp.DCCYMaxCompressedBlock);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10326

dml_get_per_surface_var_func(dcc_independent_block_l, dml_uint_t, mode_lib->mp.DCCYIndependentBlock);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10327

dml_get_per_surface_var_func(dcc_max_uncompressed_block_c, dml_uint_t, mode_lib->mp.DCCCMaxUncompressedBlock);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10328

dml_get_per_surface_var_func(dcc_max_compressed_block_c, dml_uint_t, mode_lib->mp.DCCCMaxCompressedBlock);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10329

dml_get_per_surface_var_func(dcc_independent_block_c, dml_uint_t, mode_lib->mp.DCCCIndependentBlock);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10330

dml_get_per_surface_var_func(max_active_dram_clock_change_latency_supported, dml_uint_t, mode_lib->mp.MaxActiveDRAMClockChangeLatencySupported);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10331

dml_get_per_surface_var_func(pte_buffer_mode, dml_uint_t, mode_lib->mp.PTE_BUFFER_MODE);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10332

dml_get_per_surface_var_func(bigk_fragment_size, dml_uint_t, mode_lib->mp.BIGK_FRAGMENT_SIZE);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10333

dml_get_per_surface_var_func(dpte_bytes_per_row, dml_uint_t, mode_lib->mp.PixelPTEBytesPerRow);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10334

dml_get_per_surface_var_func(meta_bytes_per_row, dml_uint_t, mode_lib->mp.MetaRowByte);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

10335

dml_get_per_surface_var_func(det_buffer_size_kbytes, dml_uint_t, mode_lib->ms.DETBufferSizeInKByte);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

105

dml_uint_t MaximumPixelsPerLinePerDSCUnit,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

106

dml_uint_t HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1111

s->DPPCycles = (dml_uint_t)(p->DPPCLKDelaySubtotalPlusCNVCFormater + p->DPPCLKDelaySCL);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1113

s->DPPCycles = (dml_uint_t)(p->DPPCLKDelaySubtotalPlusCNVCFormater + p->DPPCLKDelaySCLLBOnly);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1115

s->DPPCycles = (dml_uint_t)(s->DPPCycles + p->myPipe->NumberOfCursors * p->DPPCLKDelayCNVCCursor);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1117

s->DISPCLKCycles = (dml_uint_t)p->DISPCLKDelaySubtotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1122

*p->DSTXAfterScaler = (dml_uint_t) dml_round(s->DPPCycles * p->myPipe->PixelClock / p->myPipe->Dppclk + s->DISPCLKCycles * p->myPipe->PixelClock / p->myPipe->Dispclk + p->DSCDelay, 1.0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1123

*p->DSTXAfterScaler = (dml_uint_t) dml_round(*p->DSTXAfterScaler + (p->myPipe->ODMMode != dml_odm_mode_bypass ? 18 : 0) + (p->myPipe->DPPPerSurface - 1) * p->DPP_RECOUT_WIDTH +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

113

dml_uint_t TotalNumberOfActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

114

dml_uint_t MaxNumDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1145

*p->DSTYAfterScaler = (dml_uint_t)(dml_floor(s->DSTTotalPixelsAfterScaler / p->myPipe->HTotal, 1));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1146

*p->DSTXAfterScaler = (dml_uint_t)(s->DSTTotalPixelsAfterScaler - ((dml_float_t) (*p->DSTYAfterScaler * p->myPipe->HTotal)));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

119

dml_uint_t NumberOfDSCSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

123

dml_uint_t *NumberOfDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

144

dml_uint_t HTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

145

dml_uint_t HTapsChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

146

dml_uint_t VTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

147

dml_uint_t VTapsChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

155

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

159

dml_uint_t DPPPerSurface[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1600

dml_uint_t *BytePerPixelY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1601

dml_uint_t *BytePerPixelC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1604

dml_uint_t *BlockHeight256BytesY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1605

dml_uint_t *BlockHeight256BytesC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1606

dml_uint_t *BlockWidth256BytesY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1607

dml_uint_t *BlockWidth256BytesC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1608

dml_uint_t *MacroTileHeightY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1609

dml_uint_t *MacroTileHeightC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1610

dml_uint_t *MacroTileWidthY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1611

dml_uint_t *MacroTileWidthC)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

166

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

167

dml_uint_t MALLAllocatedForDCNFinal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

169

dml_uint_t SurfaceSizeInMALL[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1741

dml_uint_t PrefetchMode,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

175

static dml_uint_t dscceComputeDelay(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

176

dml_uint_t bpc,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1779

dml_uint_t *MinPrefetchMode,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

178

dml_uint_t sliceWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1780

dml_uint_t *MaxPrefetchMode)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

179

dml_uint_t numSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1807

dml_uint_t WritebackHTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1808

dml_uint_t WritebackVTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1809

dml_uint_t WritebackSourceWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1810

dml_uint_t WritebackDestinationWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1811

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1812

dml_uint_t WritebackLineBufferSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1827

dml_uint_t WritebackVTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1828

dml_uint_t WritebackDestinationWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1829

dml_uint_t WritebackDestinationHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

183

static dml_uint_t dscComputeDelay(enum dml_output_format_class pixelFormat,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1830

dml_uint_t WritebackSourceHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1831

dml_uint_t HTotal)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1850

dml_uint_t MaxInterDCNTileRepeaters,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1855

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1856

dml_uint_t VBlank,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1857

dml_uint_t DynamicMetadataTransmittedBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1858

dml_uint_t DynamicMetadataLinesBeforeActiveRequired,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1859

dml_uint_t InterlaceEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1867

dml_uint_t *VUpdateOffsetPix,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1868

dml_uint_t *VUpdateWidthPix,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1869

dml_uint_t *VReadyOffsetPix)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1873

*VUpdateWidthPix = (dml_uint_t)(dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / Dppclk + TotalRepeaterDelayTime) * PixelClock, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1874

*VReadyOffsetPix = (dml_uint_t)(dml_ceil(dml_max(150.0 / Dppclk, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / Dppclk) * PixelClock, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1875

*VUpdateOffsetPix = (dml_uint_t)(dml_ceil(HTotal / 4.0, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1913

dml_uint_t MetaRowByteLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1914

dml_uint_t MetaRowByteChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1915

dml_uint_t meta_row_height_luma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1916

dml_uint_t meta_row_height_chroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1917

dml_uint_t PixelPTEBytesPerRowLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1918

dml_uint_t PixelPTEBytesPerRowChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1919

dml_uint_t dpte_row_height_luma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1920

dml_uint_t dpte_row_height_chroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

195

dml_uint_t SurfaceWidthLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1952

dml_uint_t GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1954

dml_uint_t HostVMMaxNonCachedPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1956

dml_uint_t HostVMMinPageSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

196

dml_uint_t SurfaceWidthChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1961

dml_uint_t TotImmediateFlipBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1968

dml_uint_t dpte_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1969

dml_uint_t meta_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

197

dml_uint_t SurfaceHeightLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1970

dml_uint_t dpte_row_height_chroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1971

dml_uint_t meta_row_height_chroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

198

dml_uint_t SurfaceHeightChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1981

dml_uint_t HostVMDynamicLevelsTrips = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

199

dml_uint_t nomDETInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

200

dml_uint_t RequestHeight256ByteLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

201

dml_uint_t RequestHeight256ByteChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

203

dml_uint_t BytePerPixelY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

204

dml_uint_t BytePerPixelC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

209

dml_uint_t *MaxUncompressedBlockLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

210

dml_uint_t *MaxUncompressedBlockChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2100

dml_uint_t SurfaceWidthLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2101

dml_uint_t SurfaceWidthChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2102

dml_uint_t SurfaceHeightLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2103

dml_uint_t SurfaceHeightChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2104

dml_uint_t nomDETInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2105

dml_uint_t RequestHeight256ByteLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2106

dml_uint_t RequestHeight256ByteChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2108

dml_uint_t BytePerPixelY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2109

dml_uint_t BytePerPixelC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

211

dml_uint_t *MaxCompressedBlockLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2114

dml_uint_t *MaxUncompressedBlockLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2115

dml_uint_t *MaxUncompressedBlockChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2116

dml_uint_t *MaxCompressedBlockLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2117

dml_uint_t *MaxCompressedBlockChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2118

dml_uint_t *IndependentBlockLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2119

dml_uint_t *IndependentBlockChroma)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

212

dml_uint_t *MaxCompressedBlockChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2121

dml_uint_t DETBufferSizeForDCC = nomDETInKByte * 1024;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2123

dml_uint_t yuv420;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2124

dml_uint_t horz_div_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2125

dml_uint_t horz_div_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2126

dml_uint_t vert_div_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2127

dml_uint_t vert_div_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2129

dml_uint_t swath_buf_size;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

213

dml_uint_t *IndependentBlockLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2133

dml_uint_t MAS_vp_horz_limit;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2134

dml_uint_t MAS_vp_vert_limit;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2135

dml_uint_t max_vp_horz_width;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2136

dml_uint_t max_vp_vert_height;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2137

dml_uint_t eff_surf_width_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2138

dml_uint_t eff_surf_width_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2139

dml_uint_t eff_surf_height_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

214

dml_uint_t *IndependentBlockChroma);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2140

dml_uint_t eff_surf_height_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2142

dml_uint_t full_swath_bytes_horz_wc_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2143

dml_uint_t full_swath_bytes_horz_wc_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2144

dml_uint_t full_swath_bytes_vert_wc_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2145

dml_uint_t full_swath_bytes_vert_wc_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2147

dml_uint_t req128_horz_wc_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2148

dml_uint_t req128_horz_wc_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2149

dml_uint_t req128_vert_wc_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2150

dml_uint_t req128_vert_wc_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2152

dml_uint_t segment_order_horz_contiguous_luma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2153

dml_uint_t segment_order_horz_contiguous_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2154

dml_uint_t segment_order_vert_contiguous_luma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2155

dml_uint_t segment_order_vert_contiguous_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

216

static dml_uint_t CalculatePrefetchSourceLines(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

218

dml_uint_t VTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2198

max_vp_horz_width = (dml_uint_t)(dml_min((dml_float_t) MAS_vp_horz_limit, detile_buf_vp_horz_limit));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2199

max_vp_vert_height = (dml_uint_t)(dml_min((dml_float_t) MAS_vp_vert_limit, detile_buf_vp_vert_limit));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

221

dml_uint_t SwathHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2216

full_swath_bytes_horz_wc_l = (dml_uint_t)(dml_ceil((dml_float_t) full_swath_bytes_horz_wc_l * 2.0 / 3.0, 256.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2217

full_swath_bytes_horz_wc_c = (dml_uint_t)(dml_ceil((dml_float_t) full_swath_bytes_horz_wc_c * 2.0 / 3.0, 256.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2218

full_swath_bytes_vert_wc_l = (dml_uint_t)(dml_ceil((dml_float_t) full_swath_bytes_vert_wc_l * 2.0 / 3.0, 256.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2219

full_swath_bytes_vert_wc_c = (dml_uint_t)(dml_ceil((dml_float_t) full_swath_bytes_vert_wc_c * 2.0 / 3.0, 256.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

224

dml_uint_t SwathWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

225

dml_uint_t ViewportHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

226

dml_uint_t ViewportXStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

227

dml_uint_t ViewportYStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

230

dml_uint_t *VInitPreFill,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

231

dml_uint_t *MaxNumSwath);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

233

static dml_uint_t CalculateVMAndRowBytes(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

236

dml_uint_t NumberOfDPPs,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

237

dml_uint_t BlockHeight256Bytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2375

static dml_uint_t CalculatePrefetchSourceLines(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2377

dml_uint_t VTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

238

dml_uint_t BlockWidth256Bytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2380

dml_uint_t SwathHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2383

dml_uint_t SwathWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2384

dml_uint_t ViewportHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2385

dml_uint_t ViewportXStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2386

dml_uint_t ViewportYStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2389

dml_uint_t *VInitPreFill,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2390

dml_uint_t *MaxNumSwath)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2393

dml_uint_t vp_start_rot = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2394

dml_uint_t sw0_tmp = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2395

dml_uint_t MaxPartialSwath = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

240

dml_uint_t SurfaceTiling,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2407

*VInitPreFill = (dml_uint_t)(dml_floor((VRatio + (dml_float_t) VTaps + 1) / 2.0, 1));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2409

*VInitPreFill = (dml_uint_t)(dml_floor((VRatio + (dml_float_t) VTaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

241

dml_uint_t BytePerPixel,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2413

vp_start_rot = SwathHeight - (((dml_uint_t) (ViewportYStart + ViewportHeight - 1) % SwathHeight) + 1);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2417

vp_start_rot = SwathHeight - (((dml_uint_t)(ViewportYStart + SwathWidth - 1) % SwathHeight) + 1);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2423

*MaxNumSwath = (dml_uint_t)(dml_ceil((*VInitPreFill - sw0_tmp) / (dml_float_t) SwathHeight, 1) + 1);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2427

MaxPartialSwath = (dml_uint_t)(dml_max(1, (dml_uint_t) (vp_start_rot + *VInitPreFill - 1) % SwathHeight));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2429

*MaxNumSwath = (dml_uint_t)(dml_ceil((*VInitPreFill - 1.0) / (dml_float_t) SwathHeight, 1) + 1);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

243

dml_uint_t SwathWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2431

MaxPartialSwath = (dml_uint_t)(dml_max(1, (dml_uint_t) (*VInitPreFill - 2) % SwathHeight));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2433

MaxPartialSwath = (dml_uint_t)(dml_max(1, (dml_uint_t) (*VInitPreFill + SwathHeight - 2) % SwathHeight));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

244

dml_uint_t ViewportHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2445

return (dml_uint_t)(numLines);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2449

static dml_uint_t CalculateVMAndRowBytes(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

245

dml_uint_t ViewportXStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2452

dml_uint_t NumberOfDPPs,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2453

dml_uint_t BlockHeight256Bytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2454

dml_uint_t BlockWidth256Bytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2456

dml_uint_t SurfaceTiling,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2457

dml_uint_t BytePerPixel,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2459

dml_uint_t SwathWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

246

dml_uint_t ViewportYStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2460

dml_uint_t ViewportHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2461

dml_uint_t ViewportXStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2462

dml_uint_t ViewportYStart,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2464

dml_uint_t GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2465

dml_uint_t GPUVMMinPageSizeKBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2466

dml_uint_t PTEBufferSizeInRequests,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2467

dml_uint_t Pitch,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2468

dml_uint_t DCCMetaPitch,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2469

dml_uint_t MacroTileWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2470

dml_uint_t MacroTileHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2473

dml_uint_t *MetaRowByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2474

dml_uint_t *PixelPTEBytesPerRow, // for bandwidth calculation

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2475

dml_uint_t *PixelPTEBytesPerRowStorage, // for PTE buffer size check

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2476

dml_uint_t *dpte_row_width_ub,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2477

dml_uint_t *dpte_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2478

dml_uint_t *dpte_row_height_linear,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2479

dml_uint_t *PixelPTEBytesPerRow_one_row_per_frame,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

248

dml_uint_t GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2480

dml_uint_t *dpte_row_width_ub_one_row_per_frame,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2481

dml_uint_t *dpte_row_height_one_row_per_frame,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2482

dml_uint_t *MetaRequestWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2483

dml_uint_t *MetaRequestHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2484

dml_uint_t *meta_row_width,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2485

dml_uint_t *meta_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2486

dml_uint_t *PixelPTEReqWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2487

dml_uint_t *PixelPTEReqHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2488

dml_uint_t *PTERequestSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2489

dml_uint_t *DPDE0BytesFrame,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

249

dml_uint_t GPUVMMinPageSizeKBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2490

dml_uint_t *MetaPTEBytesFrame)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2492

dml_uint_t MPDEBytesFrame;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2493

dml_uint_t DCCMetaSurfaceBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2494

dml_uint_t ExtraDPDEBytesFrame;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2495

dml_uint_t PDEAndMetaPTEBytesFrame;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2496

dml_uint_t MacroTileSizeBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2497

dml_uint_t vp_height_meta_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2498

dml_uint_t vp_height_dpte_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

250

dml_uint_t PTEBufferSizeInRequests,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2500

dml_uint_t PixelPTEReqWidth_linear = 0; // VBA_DELTA. VBA doesn't calculate this

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2506

*meta_row_width = (dml_uint_t)(dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, *MetaRequestWidth) - dml_floor(ViewportXStart, *MetaRequestWidth));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

251

dml_uint_t Pitch,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2510

*meta_row_width = (dml_uint_t)(dml_floor(ViewportXStart + SwathWidth + *MetaRequestWidth - 1, *MetaRequestWidth) - dml_floor(ViewportXStart, *MetaRequestWidth));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2512

*meta_row_width = (dml_uint_t)(dml_ceil(SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2514

*MetaRowByte = (dml_uint_t)(*meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2518

*meta_row_width = (dml_uint_t)(dml_floor(ViewportYStart + ViewportHeight + *MetaRequestHeight - 1, *MetaRequestHeight) - dml_floor(ViewportYStart, *MetaRequestHeight));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

252

dml_uint_t DCCMetaPitch,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2520

*meta_row_width = (dml_uint_t)(dml_ceil(SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2522

*MetaRowByte = (dml_uint_t)(*meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2526

vp_height_meta_ub = (dml_uint_t)(dml_floor(ViewportYStart + ViewportHeight + 64 * BlockHeight256Bytes - 1, 64 * BlockHeight256Bytes) - dml_floor(ViewportYStart, 64 * BlockHeight256Bytes));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2528

vp_height_meta_ub = (dml_uint_t)(dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

253

dml_uint_t MacroTileWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2530

vp_height_meta_ub = (dml_uint_t)(dml_ceil(SwathWidth - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2533

DCCMetaSurfaceBytes = (dml_uint_t)(DCCMetaPitch * vp_height_meta_ub * BytePerPixel / 256.0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2536

*MetaPTEBytesFrame = (dml_uint_t)((dml_ceil((dml_float_t) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

254

dml_uint_t MacroTileHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2552

vp_height_dpte_ub = (dml_uint_t)(dml_floor(ViewportYStart + ViewportHeight + MacroTileHeight - 1, MacroTileHeight) - dml_floor(ViewportYStart, MacroTileHeight));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2554

vp_height_dpte_ub = (dml_uint_t)(dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2556

vp_height_dpte_ub = (dml_uint_t)(dml_ceil(SwathWidth - 1, MacroTileHeight) + MacroTileHeight);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2560

*DPDE0BytesFrame = (dml_uint_t)(64 * (dml_ceil((dml_float_t) (Pitch * vp_height_dpte_ub * BytePerPixel - MacroTileSizeBytes) / (dml_float_t) (8 * 2097152), 1) + 1));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

257

dml_uint_t *MetaRowByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

258

dml_uint_t *PixelPTEBytesPerRow,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

259

dml_uint_t *PixelPTEBytesPerRowStorage, // for PTE buffer size check

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

260

dml_uint_t *dpte_row_width_ub,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

261

dml_uint_t *dpte_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2614

*dpte_row_width_ub_one_row_per_frame = (dml_uint_t)((dml_ceil(((dml_float_t)Pitch * (dml_float_t) *dpte_row_height_one_row_per_frame / (dml_float_t) *PixelPTEReqHeight - 1) / (dml_float_t) *PixelPTEReqWidth, 1) + 1) * (dml_float_t) *PixelPTEReqWidth);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2615

*PixelPTEBytesPerRow_one_row_per_frame = (dml_uint_t)((dml_float_t) *dpte_row_width_ub_one_row_per_frame / (dml_float_t) *PixelPTEReqWidth * *PTERequestSize);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2618

*dpte_row_height = (dml_uint_t)(dml_min(128, 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

262

dml_uint_t *dpte_row_height_linear,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2622

dml_print("DML::%s: dpte_row_height term 4 = %u\n", __func__, 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2625

*dpte_row_width_ub = (dml_uint_t)(dml_ceil(((dml_float_t) Pitch * (dml_float_t) *dpte_row_height - 1), (dml_float_t) *PixelPTEReqWidth) + *PixelPTEReqWidth);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2626

*PixelPTEBytesPerRow = (dml_uint_t)((dml_float_t) *dpte_row_width_ub / (dml_float_t) *PixelPTEReqWidth * *PTERequestSize);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2629

*dpte_row_height_linear = 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * PixelPTEReqWidth_linear / Pitch), 1);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

263

dml_uint_t *PixelPTEBytesPerRow_one_row_per_frame,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

264

dml_uint_t *dpte_row_width_ub_one_row_per_frame,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2641

*dpte_row_width_ub = (dml_uint_t)((dml_ceil(((dml_float_t) Pitch * (dml_float_t) *dpte_row_height / (dml_float_t) *PixelPTEReqHeight - 1) / (dml_float_t) *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2643

*dpte_row_width_ub = (dml_uint_t)(dml_floor(ViewportXStart + SwathWidth + *PixelPTEReqWidth - 1, *PixelPTEReqWidth) - dml_floor(ViewportXStart, *PixelPTEReqWidth));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2645

*dpte_row_width_ub = (dml_uint_t)((dml_ceil((dml_float_t) (SwathWidth - 1) / (dml_float_t)*PixelPTEReqWidth, 1) + 1.0) * *PixelPTEReqWidth);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

265

dml_uint_t *dpte_row_height_one_row_per_frame,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2655

*dpte_row_height = (dml_uint_t)(dml_min(*PixelPTEReqWidth, MacroTileWidth));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2658

*dpte_row_width_ub = (dml_uint_t)(dml_floor(ViewportYStart + ViewportHeight + *PixelPTEReqHeight - 1, *PixelPTEReqHeight) - dml_floor(ViewportYStart, *PixelPTEReqHeight));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

266

dml_uint_t *MetaRequestWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2660

*dpte_row_width_ub = (dml_uint_t)((dml_ceil((dml_float_t) (SwathWidth - 1) / (dml_float_t) *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2663

*PixelPTEBytesPerRow = (dml_uint_t)((dml_float_t) *dpte_row_width_ub / (dml_float_t) *PixelPTEReqHeight * *PTERequestSize);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

267

dml_uint_t *MetaRequestHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

268

dml_uint_t *meta_row_width,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

269

dml_uint_t *meta_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2695

dml_uint_t num_active_planes = dml_get_num_active_planes(display_cfg);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2698

for (dml_uint_t k = 0; k < num_active_planes; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

270

dml_uint_t *PixelPTEReqWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2708

dml_uint_t Lanes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2709

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

271

dml_uint_t *PixelPTEReqHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2710

dml_uint_t HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2716

dml_uint_t DSCInputBitPerComponent,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2717

dml_uint_t DSCSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2718

dml_uint_t AudioRate,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2719

dml_uint_t AudioLayout,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

272

dml_uint_t *PTERequestSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2724

dml_uint_t *RequiredSlots)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2727

dml_uint_t MinDSCBPP;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2729

dml_uint_t NonDSCBPP0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

273

dml_uint_t *DPDE0BytesFrame,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2730

dml_uint_t NonDSCBPP1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2731

dml_uint_t NonDSCBPP2;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

274

dml_uint_t *MetaPTEBytesFrame);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

277

dml_uint_t PrefetchMode,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2790

*RequiredSlots = (dml_uint_t)(dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2853

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

288

dml_uint_t *MinPrefetchMode,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

289

dml_uint_t *MaxPrefetchMode);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2890

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2895

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2897

s->LBLatencyHidingSourceLinesY[k] = (dml_uint_t)(dml_min((dml_float_t)p->MaxLineBufferLines, dml_floor((dml_float_t)p->LineBufferSize / (dml_float_t)p->LBBitPerPixel[k] / ((dml_float_t)p->SwathWidthY[k] / dml_max(p->HRatio[k], 1.0)), 1)) - (p->VTaps[k] - 1));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2898

s->LBLatencyHidingSourceLinesC[k] = (dml_uint_t)(dml_min((dml_float_t)p->MaxLineBufferLines, dml_floor((dml_float_t)p->LineBufferSize / (dml_float_t)p->LBBitPerPixel[k] / ((dml_float_t)p->SwathWidthC[k] / dml_max(p->HRatioChroma[k], 1.0)), 1)) - (p->VTapsChroma[k] - 1));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2918

s->LinesInDETYRoundedDownToSwath[k] = (dml_uint_t)(dml_floor(s->LinesInDETY[k], p->SwathHeightY[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2929

s->LinesInDETCRoundedDownToSwath[k] = (dml_uint_t)(dml_floor(s->LinesInDETC[k], p->SwathHeightC[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2961

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2968

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2976

for (dml_uint_t i = 0; i < p->NumberOfActiveSurfaces; ++i) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2977

for (dml_uint_t j = 0; j < p->NumberOfActiveSurfaces; ++j) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

298

dml_uint_t MetaRowByteLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

299

dml_uint_t MetaRowByteChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2992

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

300

dml_uint_t meta_row_height_luma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

301

dml_uint_t meta_row_height_chroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3013

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

302

dml_uint_t PixelPTEBytesPerRowLuma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3021

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

303

dml_uint_t PixelPTEBytesPerRowChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

304

dml_uint_t dpte_row_height_luma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

305

dml_uint_t dpte_row_height_chroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3068

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3069

s->dst_y_pstate = (dml_uint_t)(dml_ceil((p->mmSOCParameters.DRAMClockChangeLatency + p->mmSOCParameters.UrgentLatency) / (p->HTotal[k] / p->PixelClock[k]), 1));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3070

s->src_y_pstate_l = (dml_uint_t)(dml_ceil(s->dst_y_pstate * p->VRatio[k], p->SwathHeightY[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3071

s->src_y_ahead_l = (dml_uint_t)(dml_floor(p->DETBufferSizeY[k] / p->BytePerPixelDETY[k] / p->SwathWidthY[k], p->SwathHeightY[k]) + s->LBLatencyHidingSourceLinesY[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3089

s->src_y_pstate_c = (dml_uint_t)(dml_ceil(s->dst_y_pstate * p->VRatioChroma[k], p->SwathHeightC[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3090

s->src_y_ahead_c = (dml_uint_t)(dml_floor(p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k], p->SwathHeightC[k]) + s->LBLatencyHidingSourceLinesC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3092

p->SubViewportLinesNeededInMALL[k] = (dml_uint_t)(dml_max(s->sub_vp_lines_l, s->sub_vp_lines_c));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3112

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3113

dml_uint_t BytePerPixelY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3114

dml_uint_t BytePerPixelC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3117

dml_uint_t SwathWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3118

dml_uint_t SwathWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3119

dml_uint_t DPPPerSurface[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3128

dml_uint_t ReturnBusWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3138

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

314

dml_uint_t GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

316

dml_uint_t HostVMMaxNonCachedPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3169

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

318

dml_uint_t HostVMMinPageSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3182

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3190

dml_uint_t swath_width_luma_ub,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3191

dml_uint_t swath_width_chroma_ub,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3192

dml_uint_t SwathHeightY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3193

dml_uint_t SwathHeightC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3197

dml_uint_t CursorWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3198

dml_uint_t CursorBPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3203

dml_uint_t DETBufferSizeY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3204

dml_uint_t DETBufferSizeC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3213

dml_uint_t LinesInCursorBuffer;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3221

LinesInCursorBuffer = 1 << (dml_uint_t) dml_floor(dml_log2(CursorBufferSize * 1024.0 / (CursorWidth * CursorBPP / 8.0)), 1.0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

323

dml_uint_t TotImmediateFlipBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3267

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3272

dml_uint_t swath_width_luma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3273

dml_uint_t swath_width_chroma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3274

dml_uint_t DPPPerSurface[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3281

dml_uint_t BytePerPixelC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3283

dml_uint_t NumberOfCursors[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3284

dml_uint_t CursorWidth[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3285

dml_uint_t CursorBPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3286

dml_uint_t BlockWidth256BytesY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3287

dml_uint_t BlockHeight256BytesY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3288

dml_uint_t BlockWidth256BytesC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3289

dml_uint_t BlockHeight256BytesC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

330

dml_uint_t dpte_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3305

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

331

dml_uint_t meta_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

332

dml_uint_t dpte_row_height_chroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

333

dml_uint_t meta_row_height_chroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3360

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3395

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3396

dml_uint_t cursor_req_per_width;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3397

cursor_req_per_width = (dml_uint_t)(dml_ceil((dml_float_t) CursorWidth[k] * (dml_float_t) CursorBPP[k] / 256.0 / 8.0, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3423

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3425

dml_uint_t MetaChunkSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3426

dml_uint_t MinMetaChunkSizeBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3427

dml_uint_t HTotal[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3434

dml_uint_t BytePerPixelY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3435

dml_uint_t BytePerPixelC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3437

dml_uint_t dpte_row_height[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3438

dml_uint_t dpte_row_height_chroma[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3439

dml_uint_t meta_row_width[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3440

dml_uint_t meta_row_width_chroma[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3441

dml_uint_t meta_row_height[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3442

dml_uint_t meta_row_height_chroma[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3443

dml_uint_t meta_req_width[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3444

dml_uint_t meta_req_width_chroma[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3445

dml_uint_t meta_req_height[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3446

dml_uint_t meta_req_height_chroma[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3447

dml_uint_t dpte_group_bytes[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3448

dml_uint_t PTERequestSizeY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3449

dml_uint_t PTERequestSizeC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3450

dml_uint_t PixelPTEReqWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3451

dml_uint_t PixelPTEReqHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3452

dml_uint_t PixelPTEReqWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3453

dml_uint_t PixelPTEReqHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3454

dml_uint_t dpte_row_width_luma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3455

dml_uint_t dpte_row_width_chroma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

346

dml_uint_t WritebackVTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

347

dml_uint_t WritebackDestinationWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3475

dml_uint_t meta_chunk_width;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3476

dml_uint_t min_meta_chunk_width;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3477

dml_uint_t meta_chunk_per_row_int;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3478

dml_uint_t meta_row_remainder;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3479

dml_uint_t meta_chunk_threshold;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

348

dml_uint_t WritebackDestinationHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3480

dml_uint_t meta_chunks_per_row_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3481

dml_uint_t meta_chunk_width_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3482

dml_uint_t min_meta_chunk_width_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3483

dml_uint_t meta_chunk_per_row_int_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3484

dml_uint_t meta_row_remainder_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3485

dml_uint_t meta_chunk_threshold_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3486

dml_uint_t meta_chunks_per_row_ub_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3487

dml_uint_t dpte_group_width_luma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3488

dml_uint_t dpte_groups_per_row_luma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3489

dml_uint_t dpte_group_width_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

349

dml_uint_t WritebackSourceHeight,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3490

dml_uint_t dpte_groups_per_row_chroma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3492

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

350

dml_uint_t HTotal);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3507

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

353

dml_uint_t MaxInterDCNTileRepeaters,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3533

meta_chunk_per_row_int_chroma = (dml_uint_t)((dml_float_t) meta_row_width_chroma[k] / meta_chunk_width_chroma);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3559

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3562

dpte_group_width_luma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeY[k] * PixelPTEReqWidthY[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3564

dpte_group_width_luma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeY[k] * PixelPTEReqHeightY[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3568

dpte_groups_per_row_luma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_luma_ub[k] / (dml_float_t) dpte_group_width_luma / 2.0, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3570

dpte_groups_per_row_luma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_luma_ub[k] / (dml_float_t) dpte_group_width_luma, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

358

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

359

dml_uint_t VBlank,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3591

dpte_group_width_chroma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeC[k] * PixelPTEReqWidthC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3593

dpte_group_width_chroma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeC[k] * PixelPTEReqHeightC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3597

dpte_groups_per_row_chroma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_chroma_ub[k] / (dml_float_t) dpte_group_width_chroma / 2.0, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3599

dpte_groups_per_row_chroma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_chroma_ub[k] / (dml_float_t) dpte_group_width_chroma, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

360

dml_uint_t DynamicMetadataTransmittedBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

361

dml_uint_t DynamicMetadataLinesBeforeActiveRequired,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

362

dml_uint_t InterlaceEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3642

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3644

dml_uint_t GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3645

dml_uint_t HTotal[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3646

dml_uint_t BytePerPixelC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3651

dml_uint_t dpte_row_width_luma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3652

dml_uint_t dpte_row_width_chroma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3653

dml_uint_t vm_group_bytes[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3654

dml_uint_t dpde0_bytes_per_frame_ub_l[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3655

dml_uint_t dpde0_bytes_per_frame_ub_c[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3656

dml_uint_t meta_pte_bytes_per_frame_ub_l[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3657

dml_uint_t meta_pte_bytes_per_frame_ub_c[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3665

dml_uint_t num_group_per_lower_vm_stage;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3666

dml_uint_t num_req_per_lower_vm_stage;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3672

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

368

dml_uint_t *VUpdateOffsetPix,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3686

num_group_per_lower_vm_stage = (dml_uint_t) (dml_ceil((dml_float_t) dpde0_bytes_per_frame_ub_l[k] / (dml_float_t) vm_group_bytes[k], 1.0) +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3689

num_group_per_lower_vm_stage = (dml_uint_t) (dml_ceil((dml_float_t) dpde0_bytes_per_frame_ub_l[k] / (dml_float_t) vm_group_bytes[k], 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

369

dml_uint_t *VUpdateWidthPix,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3694

num_group_per_lower_vm_stage = (dml_uint_t)(dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1.0) +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3697

num_group_per_lower_vm_stage = (dml_uint_t)(dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

370

dml_uint_t *VReadyOffsetPix);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3701

num_group_per_lower_vm_stage = (dml_uint_t)(2.0 + dml_ceil((dml_float_t) (dpde0_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1) +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3706

num_group_per_lower_vm_stage = (dml_uint_t)(1.0 + dml_ceil((dml_float_t) (dpde0_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1) +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

376

dml_uint_t Lanes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

377

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3770

dml_uint_t BytePerPixelYCriticalSurface = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3772

dml_uint_t DETBufferSizeYCriticalSurface = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3774

dml_uint_t BlockWidth256BytesYCriticalSurface = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

378

dml_uint_t HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3783

dml_uint_t TotalActiveWriteback = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3795

dml_uint_t TotalNumberOfActiveOTG = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3797

dml_uint_t SingleHTotal = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3798

dml_uint_t SingleVTotal = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3804

dml_uint_t SwathSizeCriticalSurface;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3805

dml_uint_t LastChunkOfSwathSize;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3806

dml_uint_t MissingPartOfLastSwathOfDETSize;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3813

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

384

dml_uint_t DSCInputBitPerComponent,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

385

dml_uint_t DSCSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

386

dml_uint_t AudioRate,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

387

dml_uint_t AudioLayout,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3903

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

391

dml_uint_t *RequiredSlotsSingle);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

398

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

3985

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

399

dml_uint_t BytePerPixelY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

400

dml_uint_t BytePerPixelC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4000

*p->NumberOfStutterBurstsPerFrame = (*p->StutterEfficiencyNotIncludingVBlank > 0 ? (dml_uint_t)(dml_ceil(VActiveTimeCriticalSurface / *p->StutterPeriod, 1)) : 0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4001

*p->Z8NumberOfStutterBurstsPerFrame = (*p->Z8StutterEfficiencyNotIncludingVBlank > 0 ? (dml_uint_t)(dml_ceil(VActiveTimeCriticalSurface / *p->StutterPeriod, 1)) : 0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4016

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

403

dml_uint_t SwathWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

404

dml_uint_t SwathWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

405

dml_uint_t DPPPerSurface[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4066

SwathSizeCriticalSurface = (dml_uint_t)(BytePerPixelYCriticalSurface * SwathHeightYCriticalSurface * dml_ceil(SwathWidthYCriticalSurface, BlockWidth256BytesYCriticalSurface));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4068

MissingPartOfLastSwathOfDETSize = (dml_uint_t)(dml_ceil(DETBufferSizeYCriticalSurface, SwathSizeCriticalSurface) - DETBufferSizeYCriticalSurface);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4088

dml_uint_t MaximumSwathHeightY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4089

dml_uint_t MaximumSwathHeightC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4090

dml_uint_t RoundedUpMaxSwathSizeBytesY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4091

dml_uint_t RoundedUpMaxSwathSizeBytesC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4092

dml_uint_t RoundedUpSwathSizeBytesY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4093

dml_uint_t RoundedUpSwathSizeBytesC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4094

dml_uint_t SwathWidthSingleDPP[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4095

dml_uint_t SwathWidthSingleDPPChroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4097

dml_uint_t TotalActiveDPP = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4099

dml_uint_t SurfaceDoingUnboundedRequest = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4101

dml_uint_t DETBufferSizeInKByteForSwathCalculation;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4108

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

414

dml_uint_t ReturnBusWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4149

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4150

RoundedUpMaxSwathSizeBytesY[k] = (dml_uint_t)(p->swath_width_luma_ub[k] * p->BytePerPixDETY[k] * MaximumSwathHeightY[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4151

RoundedUpMaxSwathSizeBytesC[k] = (dml_uint_t)(p->swath_width_chroma_ub[k] * p->BytePerPixDETC[k] * MaximumSwathHeightC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4164

RoundedUpMaxSwathSizeBytesY[k] = (dml_uint_t)(dml_ceil((dml_float_t) RoundedUpMaxSwathSizeBytesY[k], 256));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4165

RoundedUpMaxSwathSizeBytesC[k] = (dml_uint_t)(dml_ceil((dml_float_t) RoundedUpMaxSwathSizeBytesC[k], 256));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4169

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

421

dml_uint_t swath_width_luma_ub,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4215

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

422

dml_uint_t swath_width_chroma_ub,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

423

dml_uint_t SwathHeightY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

424

dml_uint_t SwathHeightC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4268

p->DETBufferSizeY[k] = (dml_uint_t)(dml_floor(p->DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

428

dml_uint_t CursorWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

429

dml_uint_t CursorBPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4298

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4302

dml_uint_t ViewportWidth[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4303

dml_uint_t ViewportHeight[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4304

dml_uint_t ViewportXStart[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4305

dml_uint_t ViewportYStart[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4306

dml_uint_t ViewportXStartC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4307

dml_uint_t ViewportYStartC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4308

dml_uint_t SurfaceWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4309

dml_uint_t SurfaceWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4310

dml_uint_t SurfaceHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4311

dml_uint_t SurfaceHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4313

dml_uint_t BytePerPixY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4314

dml_uint_t BytePerPixC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4315

dml_uint_t Read256BytesBlockHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4316

dml_uint_t Read256BytesBlockHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4317

dml_uint_t Read256BytesBlockWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4318

dml_uint_t Read256BytesBlockWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4319

dml_uint_t BlendingAndTiming[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4320

dml_uint_t HActive[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4322

dml_uint_t DPPPerSurface[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4325

dml_uint_t SwathWidthSingleDPPY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4326

dml_uint_t SwathWidthSingleDPPC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4327

dml_uint_t SwathWidthY[], // per-pipe

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4328

dml_uint_t SwathWidthC[], // per-pipe

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4329

dml_uint_t MaximumSwathHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4330

dml_uint_t MaximumSwathHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4331

dml_uint_t swath_width_luma_ub[], // per-pipe

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4332

dml_uint_t swath_width_chroma_ub[]) // per-pipe

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4335

dml_uint_t surface_width_ub_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4336

dml_uint_t surface_height_ub_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4337

dml_uint_t surface_width_ub_c = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4338

dml_uint_t surface_height_ub_c = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

434

dml_uint_t DETBufferSizeY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4345

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

435

dml_uint_t DETBufferSizeC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4359

for (dml_uint_t j = 0; j < NumberOfActiveSurfaces; ++j) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4369

SwathWidthY[k] = (dml_uint_t)(dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k], true)));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4371

SwathWidthY[k] = (dml_uint_t)(dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k], true)));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

44

dml_uint_t *BytePerPixelY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4400

surface_width_ub_l = (dml_uint_t)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4401

surface_height_ub_l = (dml_uint_t)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4407

swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_l, dml_floor(ViewportXStart[k] + SwathWidthY[k] + Read256BytesBlockWidthY[k] - 1, Read256BytesBlockWidthY[k]) - dml_floor(ViewportXStart[k], Read256BytesBlockWidthY[k])));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4409

swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4412

surface_width_ub_c = (dml_uint_t)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4414

swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_c, dml_floor(ViewportXStartC[k] + SwathWidthC[k] + Read256BytesBlockWidthC[k] - 1, Read256BytesBlockWidthC[k]) - dml_floor(ViewportXStartC[k], Read256BytesBlockWidthC[k])));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4416

swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4426

swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] + SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1, Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k])));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4428

swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4431

surface_height_ub_c = (dml_uint_t)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4433

swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_c, dml_floor(ViewportYStartC[k] + SwathWidthC[k] + Read256BytesBlockHeightC[k] - 1, Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], Read256BytesBlockHeightC[k])));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4435

swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4463

dml_uint_t RoundTripPingLatencyCycles,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4464

dml_uint_t ReorderingBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4466

dml_uint_t TotalNumberOfActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4467

dml_uint_t PixelChunkSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4468

dml_uint_t TotalNumberOfDCCActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4469

dml_uint_t MetaChunkSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

447

dml_uint_t DSCSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4473

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4474

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4475

dml_uint_t dpte_group_bytes[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4477

dml_uint_t HostVMMinPageSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4478

dml_uint_t HostVMMaxNonCachedPageTableLevels)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

448

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

449

dml_uint_t HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

45

dml_uint_t *BytePerPixelC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

450

dml_uint_t AudioRate,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

451

dml_uint_t AudioLayoutSingle);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4511

static dml_uint_t CalculateHostVMDynamicLevels(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4514

dml_uint_t HostVMMinPageSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4515

dml_uint_t HostVMMaxNonCachedPageTableLevels)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4517

dml_uint_t HostVMDynamicLevels = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4523

HostVMDynamicLevels = (dml_uint_t) dml_max(0, (dml_float_t) HostVMMaxNonCachedPageTableLevels - 1);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4525

HostVMDynamicLevels = (dml_uint_t) dml_max(0, (dml_float_t) HostVMMaxNonCachedPageTableLevels - 2);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4532

static dml_uint_t CalculateExtraLatencyBytes(dml_uint_t ReorderingBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4533

dml_uint_t TotalNumberOfActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4534

dml_uint_t PixelChunkSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4535

dml_uint_t TotalNumberOfDCCActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4536

dml_uint_t MetaChunkSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4539

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4540

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4541

dml_uint_t dpte_group_bytes[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4543

dml_uint_t HostVMMinPageSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4544

dml_uint_t HostVMMaxNonCachedPageTableLevels)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4546

dml_uint_t HostVMDynamicLevels = CalculateHostVMDynamicLevels(GPUVMEnable, HostVMEnable, HostVMMinPageSize, HostVMMaxNonCachedPageTableLevels);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4550

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4554

return (dml_uint_t)(ret);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

458

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4580

dml_uint_t DSCSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4581

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4582

dml_uint_t HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4583

dml_uint_t AudioRate,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4584

dml_uint_t AudioLayout)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4603

for (dml_uint_t j = 0; j < 2; ++j) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4607

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4611

for (dml_uint_t k = 0; k <= p->NumberOfActiveSurfaces - 1; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4623

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

463

dml_uint_t swath_width_luma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

464

dml_uint_t swath_width_chroma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

465

dml_uint_t DPPPerSurface[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4691

for (dml_uint_t k = 0; k <= p->NumberOfActiveSurfaces - 1; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4695

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4712

dml_uint_t TotalNumberOfActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

472

dml_uint_t BytePerPixelC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4727

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4728

dml_uint_t MALLAllocatedForDCN,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4732

dml_uint_t ViewportXStartY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4733

dml_uint_t ViewportYStartY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4734

dml_uint_t ViewportXStartC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4735

dml_uint_t ViewportYStartC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4736

dml_uint_t ViewportWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4737

dml_uint_t ViewportHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4738

dml_uint_t BytesPerPixelY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4739

dml_uint_t ViewportWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

474

dml_uint_t NumberOfCursors[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4740

dml_uint_t ViewportHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4741

dml_uint_t BytesPerPixelC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4742

dml_uint_t SurfaceWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4743

dml_uint_t SurfaceWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4744

dml_uint_t SurfaceHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4745

dml_uint_t SurfaceHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4746

dml_uint_t Read256BytesBlockWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4747

dml_uint_t Read256BytesBlockWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4748

dml_uint_t Read256BytesBlockHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4749

dml_uint_t Read256BytesBlockHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

475

dml_uint_t CursorWidth[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4750

dml_uint_t ReadBlockWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4751

dml_uint_t ReadBlockWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4752

dml_uint_t ReadBlockHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4753

dml_uint_t ReadBlockHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4756

dml_uint_t SurfaceSizeInMALL[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4759

dml_uint_t TotalSurfaceSizeInMALL = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

476

dml_uint_t CursorBPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4761

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4763

SurfaceSizeInMALL[k] = (dml_uint_t)(dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1, ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k], ReadBlockWidthY[k])) *

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4768

SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

477

dml_uint_t BlockWidth256BytesY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4773

SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4777

SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

478

dml_uint_t BlockHeight256BytesY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4783

SurfaceSizeInMALL[k] = (dml_uint_t)(dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) * dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * BytesPerPixelY[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4785

SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

479

dml_uint_t BlockWidth256BytesC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4790

SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4795

SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

48

dml_uint_t *BlockHeight256BytesY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

480

dml_uint_t BlockHeight256BytesC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4803

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4811

dml_uint_t DETSizeOverride[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4814

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4816

dml_uint_t nomDETInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4817

dml_uint_t MaxTotalDETInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4818

dml_uint_t ConfigReturnBufferSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4819

dml_uint_t MinCompressedBufferSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4820

dml_uint_t ConfigReturnBufferSegmentSizeInkByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4821

dml_uint_t CompressedBufferSegmentSizeInkByteFinal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4825

dml_uint_t RoundedUpMaxSwathSizeBytesY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4826

dml_uint_t RoundedUpMaxSwathSizeBytesC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4827

dml_uint_t DPPPerSurface[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4829

dml_uint_t DETBufferSizeInKByte[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4830

dml_uint_t *CompressedBufferSizeInkByte)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4832

dml_uint_t DETBufferSizePoolInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4833

dml_uint_t NextDETBufferPieceInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4836

dml_uint_t NextSurfaceToAssignDETPiece;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4839

dml_uint_t max_minDET;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4840

dml_uint_t minDET;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4841

dml_uint_t minDET_pipe;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4859

DETBufferSizeInKByte[0] = (dml_uint_t) dml_max(128.0, dml_ceil(2.0 * ((dml_float_t) RoundedUpMaxSwathSizeBytesY[0] + (dml_float_t) RoundedUpMaxSwathSizeBytesC[0]) / 1024.0, ConfigReturnBufferSegmentSizeInkByte));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4864

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4890

minDET_pipe = (dml_uint_t)(dml_max(128, dml_ceil(((dml_float_t)RoundedUpMaxSwathSizeBytesY[k] + (dml_float_t)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, ConfigReturnBufferSegmentSizeInkByte)));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

49

dml_uint_t *BlockHeight256BytesC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4915

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4921

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4928

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4944

for (dml_uint_t j = 0; j < NumberOfActiveSurfaces; ++j) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4948

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

496

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4978

NextDETBufferPieceInKByte = (dml_uint_t)(dml_min(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

498

dml_uint_t MetaChunkSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

499

dml_uint_t MinMetaChunkSizeBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

50

dml_uint_t *BlockWidth256BytesY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

500

dml_uint_t HTotal[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5011

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5020

dml_uint_t ConfigReturnBufferSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5021

dml_uint_t ConfigReturnBufferSegmentSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5022

dml_uint_t ROBBufferSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5023

dml_uint_t MaxNumDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5025

dml_uint_t nomDETInKByteOverrideValue, // VBA_DELTA

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5028

dml_uint_t *MaxTotalDETInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5029

dml_uint_t *nomDETInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5030

dml_uint_t *MinCompressedBufferSizeInKByte)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5033

*nomDETInKByte = (dml_uint_t)(dml_floor((dml_float_t) *MaxTotalDETInKByte / (dml_float_t) MaxNumDPP, ConfigReturnBufferSegmentSizeInKByte));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5059

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

507

dml_uint_t BytePerPixelY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

508

dml_uint_t BytePerPixelC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

51

dml_uint_t *BlockWidth256BytesC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

510

dml_uint_t dpte_row_height[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

511

dml_uint_t dpte_row_height_chroma[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

512

dml_uint_t meta_row_width[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

513

dml_uint_t meta_row_width_chroma[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

514

dml_uint_t meta_row_height[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

515

dml_uint_t meta_row_height_chroma[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

516

dml_uint_t meta_req_width[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

517

dml_uint_t meta_req_width_chroma[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

518

dml_uint_t meta_req_height[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

519

dml_uint_t meta_req_height_chroma[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

52

dml_uint_t *MacroTileHeightY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

520

dml_uint_t dpte_group_bytes[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

521

dml_uint_t PTERequestSizeY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

522

dml_uint_t PTERequestSizeC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

523

dml_uint_t PixelPTEReqWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

524

dml_uint_t PixelPTEReqHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

525

dml_uint_t PixelPTEReqWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5258

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

526

dml_uint_t PixelPTEReqHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5264

p->BIGK_FRAGMENT_SIZE[k] = (dml_uint_t)(dml_log2(p->GPUVMMinPageSizeKBytes[k] * 1024) - 12);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5267

for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

527

dml_uint_t dpte_row_width_luma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

528

dml_uint_t dpte_row_width_chroma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

53

dml_uint_t *MacroTileHeightC,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5349

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5350

dml_uint_t HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5353

dml_uint_t DSCInputBitPerComponent,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5354

dml_uint_t NumberOfDSCSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5356

dml_uint_t AudioSampleLayout,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5360

dml_uint_t OutputLinkDPLanes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5369

dml_uint_t *RequiredSlots)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5372

dml_uint_t dummy;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5385

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &dummy);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

54

dml_uint_t *MacroTileWidthY,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5411

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5416

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5424

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5430

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5438

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5443

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5453

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5461

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5469

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5478

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5486

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

549

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5495

OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

55

dml_uint_t *MacroTileWidthC);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5508

dml_uint_t MaximumPixelsPerLinePerDSCUnit,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5509

dml_uint_t HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

551

dml_uint_t GPUVMMaxPageTableLevels,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5516

dml_uint_t TotalNumberOfActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5517

dml_uint_t MaxNumDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

552

dml_uint_t HTotal[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5522

dml_uint_t NumberOfDSCSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5526

dml_uint_t *NumberOfDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

553

dml_uint_t BytePerPixelC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

558

dml_uint_t dpte_row_width_luma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

559

dml_uint_t dpte_row_width_chroma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

560

dml_uint_t vm_group_bytes[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

561

dml_uint_t dpde0_bytes_per_frame_ub_l[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

562

dml_uint_t dpde0_bytes_per_frame_ub_c[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

563

dml_uint_t meta_pte_bytes_per_frame_ub_l[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

564

dml_uint_t meta_pte_bytes_per_frame_ub_c[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5646

dml_uint_t HTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5647

dml_uint_t HTapsChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5648

dml_uint_t VTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5649

dml_uint_t VTapsChroma,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5691

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5695

dml_uint_t DPPPerSurface[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5702

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5709

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5716

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5717

dml_uint_t MALLAllocatedForDCNFinal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5719

dml_uint_t SurfaceSizeInMALL[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5726

dml_uint_t SurfaceToAddToMALL;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5728

dml_uint_t TotalSurfaceSizeInMALL;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5731

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5745

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

582

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

586

dml_uint_t ViewportWidth[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

587

dml_uint_t ViewportHeight[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5870

static dml_uint_t DSCDelayRequirement(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5873

dml_uint_t DSCInputBitPerComponent,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5875

dml_uint_t HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5876

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5877

dml_uint_t NumberOfDSCSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

588

dml_uint_t ViewportXStart[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5883

dml_uint_t DSCDelayRequirement_val = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5887

DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)(dml_ceil((dml_float_t) HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5888

(dml_uint_t) (NumberOfDSCSlices / 4.0), OutputFormat, Output) + dscComputeDelay(OutputFormat, Output);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

589

dml_uint_t ViewportYStart[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5890

DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)(dml_ceil((dml_float_t) HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5891

(dml_uint_t) (NumberOfDSCSlices / 2.0), OutputFormat, Output) + dscComputeDelay(OutputFormat, Output);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5893

DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)((dml_float_t) dml_ceil(HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5896

DSCDelayRequirement_val = (dml_uint_t)(DSCDelayRequirement_val + (HTotal - HActive) * dml_ceil((dml_float_t) DSCDelayRequirement_val / (dml_float_t) HActive, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5897

DSCDelayRequirement_val = (dml_uint_t)(DSCDelayRequirement_val * PixelClock / PixelClockBackEnd);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

590

dml_uint_t ViewportXStartC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

591

dml_uint_t ViewportYStartC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5919

static noinline_for_stack dml_bool_t CalculateVActiveBandwithSupport(dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

592

dml_uint_t SurfaceWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5927

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

593

dml_uint_t SurfaceWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5936

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

594

dml_uint_t SurfaceHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5942

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

595

dml_uint_t SurfaceHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5958

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

597

dml_uint_t BytePerPixY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5971

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

598

dml_uint_t BytePerPixC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5986

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

599

dml_uint_t Read256BytesBlockHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5993

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

600

dml_uint_t Read256BytesBlockHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6000

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

601

dml_uint_t Read256BytesBlockWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

602

dml_uint_t Read256BytesBlockWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6024

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

603

dml_uint_t BlendingAndTiming[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6032

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

604

dml_uint_t HActive[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6042

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

606

dml_uint_t DPPPerSurface[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6070

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6084

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

609

dml_uint_t SwathWidthSingleDPPY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6099

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

610

dml_uint_t SwathWidthSingleDPPC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

611

dml_uint_t SwathWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

612

dml_uint_t SwathWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

613

dml_uint_t MaximumSwathHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6137

for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

614

dml_uint_t MaximumSwathHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

615

dml_uint_t swath_width_luma_ub[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

616

dml_uint_t swath_width_chroma_ub[]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6162

static dml_uint_t MicroSecToVertLines(dml_uint_t num_us, dml_uint_t h_total, dml_float_t pixel_clock)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6164

dml_uint_t lines_time_in_ns = 1000.0 * (h_total * 1000.0) / (pixel_clock * 1000.0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6171

static dml_uint_t CalculateMaxVStartup(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6172

dml_uint_t plane_idx,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6174

dml_uint_t vblank_nom_default_us,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6178

dml_uint_t vblank_size = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6179

dml_uint_t max_vstartup_lines = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6180

const dml_uint_t max_allowed_vblank_nom = 1023;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6183

dml_uint_t vblank_actual = timing->VTotal[plane_idx] - timing->VActive[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6185

dml_uint_t vblank_nom_default_in_line = MicroSecToVertLines(vblank_nom_default_us, timing->HTotal[plane_idx],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6187

dml_uint_t vblank_nom_input = (dml_uint_t)dml_min(vblank_actual, vblank_nom_default_in_line);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

619

dml_uint_t RoundTripPingLatencyCycles,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6193

dml_uint_t vblank_nom_vsync_capped = dml_max(vblank_nom_input,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6195

dml_uint_t vblank_nom_max_allowed_capped = dml_min(vblank_nom_vsync_capped, max_allowed_vblank_nom);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6196

dml_uint_t vblank_avail = (vblank_nom_max_allowed_capped == 0) ?

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6199

vblank_size = (dml_uint_t) dml_min(vblank_actual, vblank_avail);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

62

dml_uint_t WritebackHTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

620

dml_uint_t ReorderingBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6202

max_vstartup_lines = (dml_uint_t) (dml_floor(vblank_size/2.0, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6204

max_vstartup_lines = vblank_size - (dml_uint_t) dml_max(1.0, dml_ceil(write_back_delay_us/line_time_us, 1.0));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6214

max_vstartup_lines = (dml_uint_t) dml_min(max_vstartup_lines, DML_MAX_VSTARTUP_START);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

622

dml_uint_t TotalNumberOfActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6220

dml_uint_t j,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6221

dml_uint_t k)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

623

dml_uint_t PixelChunkSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6230

CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (dml_uint_t)(mode_lib->ms.SwathWidthYThisState[k] / mode_lib->ms.cache_display_cfg.plane.HRatio[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

624

dml_uint_t TotalNumberOfDCCActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

625

dml_uint_t MetaChunkSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6276

dml_uint_t j, k;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

629

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

63

dml_uint_t WritebackVTaps,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

630

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

631

dml_uint_t dpte_group_bytes[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

633

dml_uint_t HostVMMinPageSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

634

dml_uint_t HostVMMaxNonCachedPageTableLevels);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

636

static dml_uint_t CalculateExtraLatencyBytes(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

637

dml_uint_t ReorderingBytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

638

dml_uint_t TotalNumberOfActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

639

dml_uint_t PixelChunkSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6399

CalculatePrefetchSchedule_params->VStartup = (dml_uint_t)(dml_min(s->MaxVStartup, s->MaximumVStartup[j][k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

64

dml_uint_t WritebackSourceWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

640

dml_uint_t TotalNumberOfDCCActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

641

dml_uint_t MetaChunkSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

644

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

645

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

646

dml_uint_t dpte_group_bytes[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

648

dml_uint_t HostVMMinPageSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

649

dml_uint_t HostVMMaxNonCachedPageTableLevels);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

65

dml_uint_t WritebackDestinationWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

66

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

662

dml_uint_t TotalNumberOfActiveDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

667

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

668

dml_uint_t MALLAllocatedForDCN,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

67

dml_uint_t WritebackLineBufferSize,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

672

dml_uint_t ViewportXStartY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6722

dml_uint_t j, k, m;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

673

dml_uint_t ViewportYStartY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

674

dml_uint_t ViewportXStartC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

675

dml_uint_t ViewportYStartC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

676

dml_uint_t ViewportWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

677

dml_uint_t ViewportHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

678

dml_uint_t BytesPerPixelY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

679

dml_uint_t ViewportWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

680

dml_uint_t ViewportHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

681

dml_uint_t BytesPerPixelC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

682

dml_uint_t SurfaceWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

683

dml_uint_t SurfaceWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

684

dml_uint_t SurfaceHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

685

dml_uint_t SurfaceHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6856

for (k = 0; k <= (dml_uint_t) mode_lib->ms.num_active_planes - 1; k++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

686

dml_uint_t Read256BytesBlockWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6863

if (s->TotalNumberOfActiveWriteback > (dml_uint_t) mode_lib->ms.ip.max_num_wb) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

687

dml_uint_t Read256BytesBlockWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6875

|| mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] > (dml_uint_t) mode_lib->ms.ip.writeback_max_hscl_taps

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6876

|| mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k] > (dml_uint_t) mode_lib->ms.ip.writeback_max_vscl_taps

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6877

|| mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] > (dml_uint_t) mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6878

|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] > (dml_uint_t) mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

688

dml_uint_t Read256BytesBlockHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

689

dml_uint_t Read256BytesBlockHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

690

dml_uint_t ReadBlockWidthY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

691

dml_uint_t ReadBlockWidthC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

692

dml_uint_t ReadBlockHeightY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6924

s->MaximumSwathWidthSupportChroma = (dml_uint_t)(s->MaximumSwathWidthSupportLuma / 2.0);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

693

dml_uint_t ReadBlockHeightC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6952

mode_lib->ms.support.NumberOfDSCSlices[k] = (dml_uint_t)(dml_ceil(mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 600, 4));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

696

dml_uint_t SurfaceSizeInMALL[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

700

dml_uint_t DETSizeOverride[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

703

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

705

dml_uint_t nomDETInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

706

dml_uint_t MaxTotalDETInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

707

dml_uint_t ConfigReturnBufferSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

708

dml_uint_t MinCompressedBufferSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

709

dml_uint_t ConfigReturnBufferSegmentSizeInkByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

710

dml_uint_t CompressedBufferSegmentSizeInkByteFinal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

714

dml_uint_t RotesY[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

715

dml_uint_t RoundedUpMaxSwathSizeBytesC[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7154

} else if (mode_lib->ms.TotalNumberOfActiveDPP[j] < (dml_uint_t) mode_lib->ms.ip.max_num_dpp) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7157

mode_lib->ms.TotalNumberOfActiveDPP[j] = (dml_uint_t) mode_lib->ms.TotalNumberOfActiveDPP[j] + 1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

716

dml_uint_t DPPPerSurface[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7167

for (k = 0; k < (dml_uint_t) mode_lib->ms.num_active_planes; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

718

dml_uint_t DETBufferSizeInKByte[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7182

while (!(mode_lib->ms.TotalNumberOfActiveDPP[j] >= (dml_uint_t) mode_lib->ms.ip.max_num_dpp || mode_lib->ms.TotalNumberOfSingleDPPSurfaces[j] == 0)) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

719

dml_uint_t *CompressedBufferSizeInkByte);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

722

dml_uint_t ConfigReturnBufferSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

723

dml_uint_t ConfigReturnBufferSegmentSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

724

dml_uint_t ROBBufferSizeInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7244

if (mode_lib->ms.TotalNumberOfActiveDPP[j] > (dml_uint_t) mode_lib->ms.ip.max_num_dpp) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

725

dml_uint_t MaxNumDPP,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7269

mode_lib->ms.support.NumberOfOTGSupport = (s->TotalNumberOfActiveOTG <= (dml_uint_t) mode_lib->ms.ip.max_num_otg);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

727

dml_uint_t nomDETInKByteOverrideValue,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7270

mode_lib->ms.support.NumberOfHDMIFRLSupport = (s->TotalNumberOfActiveHDMIFRL <= (dml_uint_t) mode_lib->ms.ip.max_num_hdmi_frl_outputs);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7271

mode_lib->ms.support.NumberOfDP2p0Support = (s->TotalNumberOfActiveDP2p0 <= (dml_uint_t) mode_lib->ms.ip.max_num_dp2p0_streams && s->TotalNumberOfActiveDP2p0Outputs <= (dml_uint_t) mode_lib->ms.ip.max_num_dp2p0_outputs);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7280

|| mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] > (dml_uint_t) mode_lib->ms.ip.maximum_dsc_bits_per_component

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

730

dml_uint_t *MaxTotalDETInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

731

dml_uint_t *nomDETInKByte,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

732

dml_uint_t *MinCompressedBufferSizeInKByte);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

734

static dml_uint_t DSCDelayRequirement(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

737

dml_uint_t DSCInputBitPerComponent,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

739

dml_uint_t HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

740

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

741

dml_uint_t NumberOfDSCSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7449

if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 4 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7455

if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 2 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7461

if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7469

if (s->TotalDSCUnitsRequired > (dml_uint_t) mode_lib->ms.ip.num_dsc) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

748

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

756

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

762

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

775

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7892

s->MaxVStartupAllPlanes[j] = (dml_uint_t)(dml_max(s->MaxVStartupAllPlanes[j], s->MaximumVStartup[j][k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

790

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7900

s->ReorderingBytes = (dml_uint_t)(mode_lib->ms.soc.num_chans * dml_max3(mode_lib->ms.soc.urgent_out_of_order_return_per_channel_pixel_only_bytes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

798

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

807

dml_uint_t NumberOfActiveSurfaces,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

82

dml_uint_t HTotal,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

821

dml_uint_t NumberOfDPP[],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

83

dml_uint_t HActive,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8302

dml_uint_t j = 0, k = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

839

static dml_uint_t dscceComputeDelay(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

840

dml_uint_t bpc,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

842

dml_uint_t sliceWidth,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

843

dml_uint_t numSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

856

dml_uint_t rcModelSize = 8192;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

859

dml_uint_t pixelsPerClock, lstall, D, initalXmitDelay, w, s, ix, wx, p, l0, a, ax, L,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

86

dml_uint_t DSCInputBitPerComponent,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

87

dml_uint_t NumberOfDSCSlices,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

873

initalXmitDelay = (dml_uint_t)(dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock, 1));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8765

s->ReorderBytes = (dml_uint_t)(mode_lib->ms.soc.num_chans * dml_max3(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

89

dml_uint_t AudioSampleLayout,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8920

s->MaxVStartupAllPlanes = (dml_uint_t)(dml_max(s->MaxVStartupAllPlanes, s->MaxVStartupLines[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9001

CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (dml_uint_t)(locals->SwathWidthY[k] / mode_lib->ms.cache_display_cfg.plane.HRatio[k]);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9004

CalculatePrefetchSchedule_params->VStartup = (dml_uint_t)(dml_min(s->VStartupLines, s->MaxVStartupLines[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9058

locals->VStartup[k] = (dml_uint_t)(dml_min(s->VStartupLines, s->MaxVStartupLines[k]));

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

921

static dml_uint_t dscComputeDelay(enum dml_output_format_class pixelFormat, enum dml_output_encoder_class Output)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

923

dml_uint_t Delay = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

93

dml_uint_t OutputLinkDPLanes,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9835

dml_uint_t dummy_integer[1];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9917

dml_uint_t *dpte_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9918

dml_uint_t *meta_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9924

dml_uint_t pitch,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9925

dml_uint_t GPUVMMinPageSizeKBytes)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9927

dml_uint_t BytePerPixelY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9928

dml_uint_t BytePerPixelC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9931

dml_uint_t BlockHeight256BytesY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9932

dml_uint_t BlockHeight256BytesC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9933

dml_uint_t BlockWidth256BytesY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9934

dml_uint_t BlockWidth256BytesC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9935

dml_uint_t MacroTileWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9936

dml_uint_t MacroTileWidthC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9937

dml_uint_t MacroTileHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9938

dml_uint_t MacroTileHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9940

dml_uint_t BytePerPixel;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9941

dml_uint_t BlockHeight256Bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9942

dml_uint_t BlockWidth256Bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9943

dml_uint_t MacroTileWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9944

dml_uint_t MacroTileHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9945

dml_uint_t PTEBufferSizeInRequests;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9947

dml_uint_t dummy_integer[16];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

117

dml_get_var_decl(comp_buffer_size_kbytes, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

118

dml_get_var_decl(pixel_chunk_size_in_kbyte, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

119

dml_get_var_decl(alpha_pixel_chunk_size_in_kbyte, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

120

dml_get_var_decl(meta_chunk_size_in_kbyte, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

121

dml_get_var_decl(min_pixel_chunk_size_in_byte, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

122

dml_get_var_decl(min_meta_chunk_size_in_byte, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

123

dml_get_var_decl(total_immediate_flip_bytes, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

125

dml_get_per_surface_var_decl(dsc_delay, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

131

dml_get_per_surface_var_decl(dst_x_after_scaler, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

132

dml_get_per_surface_var_decl(dst_y_after_scaler, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

171

dml_get_per_surface_var_decl(dpte_group_size_in_bytes, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

172

dml_get_per_surface_var_decl(vm_group_size_in_bytes, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

173

dml_get_per_surface_var_decl(swath_height_l, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

174

dml_get_per_surface_var_decl(swath_height_c, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

175

dml_get_per_surface_var_decl(dpte_row_height_l, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

176

dml_get_per_surface_var_decl(dpte_row_height_c, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

177

dml_get_per_surface_var_decl(dpte_row_height_linear_l, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

178

dml_get_per_surface_var_decl(dpte_row_height_linear_c, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

179

dml_get_per_surface_var_decl(meta_row_height_l, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

180

dml_get_per_surface_var_decl(meta_row_height_c, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

181

dml_get_per_surface_var_decl(vstartup_calculated, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

182

dml_get_per_surface_var_decl(vupdate_offset, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

183

dml_get_per_surface_var_decl(vupdate_width, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

184

dml_get_per_surface_var_decl(vready_offset, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

185

dml_get_per_surface_var_decl(vready_at_or_after_vsync, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

186

dml_get_per_surface_var_decl(min_dst_y_next_start, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

187

dml_get_per_surface_var_decl(det_stored_buffer_size_l_bytes, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

188

dml_get_per_surface_var_decl(det_stored_buffer_size_c_bytes, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

189

dml_get_per_surface_var_decl(use_mall_for_static_screen, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

190

dml_get_per_surface_var_decl(surface_size_for_mall, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

191

dml_get_per_surface_var_decl(dcc_max_uncompressed_block_l, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

192

dml_get_per_surface_var_decl(dcc_max_uncompressed_block_c, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

193

dml_get_per_surface_var_decl(dcc_max_compressed_block_l, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

194

dml_get_per_surface_var_decl(dcc_max_compressed_block_c, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

195

dml_get_per_surface_var_decl(dcc_independent_block_l, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

196

dml_get_per_surface_var_decl(dcc_independent_block_c, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

197

dml_get_per_surface_var_decl(max_active_dram_clock_change_latency_supported, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

198

dml_get_per_surface_var_decl(pte_buffer_mode, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

199

dml_get_per_surface_var_decl(bigk_fragment_size, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

200

dml_get_per_surface_var_decl(dpte_bytes_per_row, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

201

dml_get_per_surface_var_decl(meta_bytes_per_row, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

202

dml_get_per_surface_var_decl(det_buffer_size_kbytes, dml_uint_t);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

38

dml_uint_t *dpte_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

39

dml_uint_t *meta_row_height,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

45

dml_uint_t pitch,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

46

dml_uint_t GPUVMMinPageSizeKBytes);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

66

dml_uint_t state_idx,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

71

dml_uint_t state_idx,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

75

dml_uint_t dml_mode_support_ex(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

78

dml_bool_t dml_get_is_phantom_pipe(struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h

80

#define dml_get_per_surface_var_decl(variable, type) type dml_get_##variable(struct display_mode_lib_st *mode_lib, dml_uint_t surface_idx)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1000

dml_uint_t TotalNumberOfDCCActiveDPP[2];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1002

dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1014

dml_uint_t VInitPreFillY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1015

dml_uint_t VInitPreFillC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1016

dml_uint_t MaxNumSwathY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1017

dml_uint_t MaxNumSwathC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1021

dml_uint_t BytePerPixelY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1022

dml_uint_t BytePerPixelC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1023

dml_uint_t SwathWidthY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1024

dml_uint_t SwathWidthC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1025

dml_uint_t SwathWidthSingleDPPY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1026

dml_uint_t SwathWidthSingleDPPC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1030

dml_uint_t PixelPTEBytesPerRow[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1031

dml_uint_t PDEAndMetaPTEBytesFrame[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1032

dml_uint_t MetaRowByte[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1033

dml_uint_t PrefetchSourceLinesY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1036

dml_uint_t PrefetchSourceLinesC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1039

dml_uint_t DSCDelay[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1042

dml_uint_t MacroTileWidthY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1043

dml_uint_t MacroTileWidthC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1044

dml_uint_t BlockHeight256BytesY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1045

dml_uint_t BlockHeight256BytesC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1046

dml_uint_t BlockWidth256BytesY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1047

dml_uint_t BlockWidth256BytesC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1049

dml_uint_t BlockHeightY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1050

dml_uint_t BlockHeightC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1051

dml_uint_t BlockWidthY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1052

dml_uint_t BlockWidthC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1054

dml_uint_t SurfaceSizeInTheMALL[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1063

dml_uint_t dpte_row_height[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1064

dml_uint_t dpte_row_height_linear[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1065

dml_uint_t meta_req_width[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1066

dml_uint_t meta_req_height[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1067

dml_uint_t meta_row_width[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1068

dml_uint_t meta_row_height[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1069

dml_uint_t dpte_row_width_luma_ub[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1070

dml_uint_t dpte_row_width_chroma_ub[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1071

dml_uint_t dpte_row_height_chroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1072

dml_uint_t dpte_row_height_linear_chroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1073

dml_uint_t meta_req_width_chroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1074

dml_uint_t meta_req_height_chroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1075

dml_uint_t meta_row_width_chroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1076

dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1077

dml_uint_t vm_group_bytes[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1078

dml_uint_t dpte_group_bytes[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1088

dml_uint_t swath_width_luma_ub[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1089

dml_uint_t swath_width_chroma_ub[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1090

dml_uint_t PixelPTEReqWidthY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1091

dml_uint_t PixelPTEReqHeightY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1092

dml_uint_t PTERequestSizeY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1093

dml_uint_t PixelPTEReqWidthC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1094

dml_uint_t PixelPTEReqHeightC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1095

dml_uint_t PTERequestSizeC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1100

dml_uint_t dpde0_bytes_per_frame_ub_l[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1101

dml_uint_t meta_pte_bytes_per_frame_ub_l[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1102

dml_uint_t dpde0_bytes_per_frame_ub_c[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1103

dml_uint_t meta_pte_bytes_per_frame_ub_c[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1106

dml_uint_t compbuf_reserved_space_64b;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1107

dml_uint_t compbuf_reserved_space_zs;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1108

dml_uint_t CompressedBufferSizeInkByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1132

dml_uint_t TotImmediateFlipBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1137

dml_uint_t pipe_plane[__DML_NUM_PLANES__]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1138

dml_uint_t num_active_pipes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1143

dml_uint_t PrefetchMode[__DML_NUM_PLANES__]; /// <brief prefetch mode used for prefetch support check in mode programming step

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1170

dml_uint_t DCCYMaxUncompressedBlock[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1171

dml_uint_t DCCYMaxCompressedBlock[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1172

dml_uint_t DCCYIndependentBlock[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1173

dml_uint_t DCCCMaxUncompressedBlock[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1174

dml_uint_t DCCCMaxCompressedBlock[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1175

dml_uint_t DCCCIndependentBlock[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1180

dml_uint_t NumberOfStutterBurstsPerFrame;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1182

dml_uint_t Z8NumberOfStutterBurstsPerFrame;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1186

dml_uint_t Z8NumberOfStutterBurstsPerFrameBestCase;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1193

dml_uint_t DSTYAfterScaler[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1194

dml_uint_t DSTXAfterScaler[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1238

dml_uint_t BIGK_FRAGMENT_SIZE[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1240

dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1244

dml_uint_t VStartupMin[__DML_NUM_PLANES__]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos.

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1245

dml_uint_t VStartup[__DML_NUM_PLANES__]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank))

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1246

dml_uint_t VUpdateOffsetPix[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1247

dml_uint_t VUpdateWidthPix[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1248

dml_uint_t VReadyOffsetPix[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1260

dml_uint_t DETBufferSizeInKByte[__DML_NUM_PLANES__]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1261

dml_uint_t DETBufferSizeY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1262

dml_uint_t DETBufferSizeC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1263

dml_uint_t SwathHeightY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1264

dml_uint_t SwathHeightC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1268

dml_uint_t num_states; /// <brief num of soc pwr states

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1276

dml_uint_t MaxInterDCNTileRepeaters;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1277

dml_uint_t MaxPrefetchMode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1281

dml_uint_t ReturnBusWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1282

dml_uint_t RoundTripPingLatencyCycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1283

dml_uint_t ReorderingBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1284

dml_uint_t PixelChunkSizeInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1285

dml_uint_t MetaChunkSize;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1287

dml_uint_t GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1289

dml_uint_t NumberOfActiveSurfaces;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1290

dml_uint_t HostVMMinPageSize;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1291

dml_uint_t HostVMMaxNonCachedPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1297

dml_uint_t *VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1298

dml_uint_t *VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1299

dml_uint_t *DynamicMetadataTransmittedBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1300

dml_uint_t *DynamicMetadataLinesBeforeActiveRequired;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1305

dml_uint_t (*NoOfDPP)[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1307

dml_uint_t (*MaximumVStartup)[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1308

dml_uint_t *TotalNumberOfActiveDPP;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1309

dml_uint_t *TotalNumberOfDCCActiveDPP;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1310

dml_uint_t *dpte_group_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1311

dml_uint_t (*PrefetchLinesY)[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1312

dml_uint_t (*PrefetchLinesC)[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1313

dml_uint_t (*swath_width_luma_ub_all_states)[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1314

dml_uint_t (*swath_width_chroma_ub_all_states)[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1315

dml_uint_t *BytePerPixelY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1316

dml_uint_t *BytePerPixelC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1317

dml_uint_t *HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1319

dml_uint_t (*PDEAndMetaPTEBytesPerFrame)[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1320

dml_uint_t (*DPTEBytesPerRow)[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1321

dml_uint_t (*MetaRowBytes)[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1332

dml_uint_t *PrefetchMode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1333

dml_uint_t NumberOfActiveSurfaces;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1334

dml_uint_t MaxLineBufferLines;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1335

dml_uint_t LineBufferSize;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1336

dml_uint_t WritebackInterfaceBufferSize;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1342

dml_uint_t *dpte_group_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1343

dml_uint_t *meta_row_height;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1344

dml_uint_t *meta_row_height_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1346

dml_uint_t WritebackChunkSize;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1349

dml_uint_t *DETBufferSizeY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1350

dml_uint_t *DETBufferSizeC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1351

dml_uint_t *SwathHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1352

dml_uint_t *SwathHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1353

dml_uint_t *LBBitPerPixel;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1354

dml_uint_t *SwathWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1355

dml_uint_t *SwathWidthC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1358

dml_uint_t *VTaps;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1359

dml_uint_t *VTapsChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1362

dml_uint_t *HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1363

dml_uint_t *VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1364

dml_uint_t *VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1366

dml_uint_t *BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1367

dml_uint_t *DPPPerSurface;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1370

dml_uint_t *DSTXAfterScaler;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1371

dml_uint_t *DSTYAfterScaler;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1374

dml_uint_t *WritebackDestinationWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1375

dml_uint_t *WritebackDestinationHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1376

dml_uint_t *WritebackSourceHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1378

dml_uint_t CompressedBufferSizeInkByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1384

dml_uint_t *SubViewportLinesNeededInMALL;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1392

dml_uint_t NumberOfActiveSurfaces;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1394

dml_uint_t *SurfaceSizeInMALL;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1395

dml_uint_t PTEBufferSizeInRequestsLuma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1396

dml_uint_t PTEBufferSizeInRequestsChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1397

dml_uint_t DCCMetaBufferSizeBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1400

dml_uint_t MALLAllocatedForDCN;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1401

dml_uint_t *SwathWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1402

dml_uint_t *SwathWidthC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1405

dml_uint_t HostVMMaxNonCachedPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1406

dml_uint_t GPUVMMaxPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1407

dml_uint_t *GPUVMMinPageSizeKBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1408

dml_uint_t HostVMMinPageSize;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1415

dml_uint_t *dpte_row_width_luma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1416

dml_uint_t *dpte_row_width_chroma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1417

dml_uint_t *dpte_row_height_luma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1418

dml_uint_t *dpte_row_height_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1419

dml_uint_t *dpte_row_height_linear_luma; // VBA_DELTA

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1420

dml_uint_t *dpte_row_height_linear_chroma; // VBA_DELTA

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1421

dml_uint_t *meta_req_width;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1422

dml_uint_t *meta_req_width_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1423

dml_uint_t *meta_req_height;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1424

dml_uint_t *meta_req_height_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1425

dml_uint_t *meta_row_width;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1426

dml_uint_t *meta_row_width_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1427

dml_uint_t *meta_row_height;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1428

dml_uint_t *meta_row_height_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1429

dml_uint_t *vm_group_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1430

dml_uint_t *dpte_group_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1431

dml_uint_t *PixelPTEReqWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1432

dml_uint_t *PixelPTEReqHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1433

dml_uint_t *PTERequestSizeY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1434

dml_uint_t *PixelPTEReqWidthC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1435

dml_uint_t *PixelPTEReqHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1436

dml_uint_t *PTERequestSizeC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1437

dml_uint_t *dpde0_bytes_per_frame_ub_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1438

dml_uint_t *meta_pte_bytes_per_frame_ub_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1439

dml_uint_t *dpde0_bytes_per_frame_ub_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1440

dml_uint_t *meta_pte_bytes_per_frame_ub_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1441

dml_uint_t *PrefetchSourceLinesY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1442

dml_uint_t *PrefetchSourceLinesC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1443

dml_uint_t *VInitPreFillY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1444

dml_uint_t *VInitPreFillC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1445

dml_uint_t *MaxNumSwathY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1446

dml_uint_t *MaxNumSwathC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1449

dml_uint_t *PixelPTEBytesPerRow;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1450

dml_uint_t *PDEAndMetaPTEBytesFrame;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1451

dml_uint_t *MetaRowByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1456

dml_uint_t *BIGK_FRAGMENT_SIZE;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1460

dml_uint_t *DETSizeOverride;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1462

dml_uint_t ConfigReturnBufferSizeInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1463

dml_uint_t ROBBufferSizeInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1464

dml_uint_t MaxTotalDETInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1465

dml_uint_t MinCompressedBufferSizeInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1466

dml_uint_t PixelChunkSizeInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1468

dml_uint_t NumberOfActiveSurfaces;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1469

dml_uint_t nomDETInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1471

dml_uint_t ConfigReturnBufferSegmentSizeInkByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1472

dml_uint_t CompressedBufferSegmentSizeInkByteFinal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1482

dml_uint_t *ViewportWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1483

dml_uint_t *ViewportHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1484

dml_uint_t *ViewportXStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1485

dml_uint_t *ViewportYStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1486

dml_uint_t *ViewportXStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1487

dml_uint_t *ViewportYStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1488

dml_uint_t *SurfaceWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1489

dml_uint_t *SurfaceWidthC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1490

dml_uint_t *SurfaceHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1491

dml_uint_t *SurfaceHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1492

dml_uint_t *Read256BytesBlockHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1493

dml_uint_t *Read256BytesBlockHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1494

dml_uint_t *Read256BytesBlockWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1495

dml_uint_t *Read256BytesBlockWidthC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1497

dml_uint_t *BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1498

dml_uint_t *BytePerPixY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1499

dml_uint_t *BytePerPixC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1502

dml_uint_t *HActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1505

dml_uint_t *DPPPerSurface;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1506

dml_uint_t *swath_width_luma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1507

dml_uint_t *swath_width_chroma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1508

dml_uint_t *SwathWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1509

dml_uint_t *SwathWidthChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1510

dml_uint_t *SwathHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1511

dml_uint_t *SwathHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1512

dml_uint_t *DETBufferSizeInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1513

dml_uint_t *DETBufferSizeY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1514

dml_uint_t *DETBufferSizeC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1516

dml_uint_t *compbuf_reserved_space_64b;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1517

dml_uint_t *compbuf_reserved_space_zs;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1518

dml_uint_t *CompressedBufferSizeInkByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1524

dml_uint_t CompressedBufferSizeInkByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1527

dml_uint_t MetaFIFOSizeInKEntries;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1528

dml_uint_t ZeroSizeBufferEntries;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1529

dml_uint_t PixelChunkSizeInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1530

dml_uint_t NumberOfActiveSurfaces;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1531

dml_uint_t ROBBufferSizeInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1535

dml_uint_t CompbufReservedSpace64B;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1536

dml_uint_t CompbufReservedSpaceZs;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1540

dml_uint_t *BlendingAndTiming;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1546

dml_uint_t *DPPPerSurface;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1547

dml_uint_t *DETBufferSizeY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1548

dml_uint_t *BytePerPixelY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1550

dml_uint_t *SwathWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1551

dml_uint_t *SwathHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1552

dml_uint_t *SwathHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1557

dml_uint_t *HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1558

dml_uint_t *VTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1562

dml_uint_t *BlockHeight256BytesY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1563

dml_uint_t *BlockWidth256BytesY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1564

dml_uint_t *BlockHeight256BytesC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1565

dml_uint_t *BlockWidth256BytesC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1566

dml_uint_t *DCCYMaxUncompressedBlock;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1567

dml_uint_t *DCCCMaxUncompressedBlock;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1568

dml_uint_t *VActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1577

dml_uint_t *NumberOfStutterBurstsPerFrame;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1580

dml_uint_t *Z8NumberOfStutterBurstsPerFrame;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1589

dml_uint_t DSCDelay;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1595

dml_uint_t DPP_RECOUT_WIDTH;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1597

dml_uint_t MaxInterDCNTileRepeaters;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1598

dml_uint_t VStartup;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1599

dml_uint_t MaxVStartup;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1600

dml_uint_t GPUVMPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1603

dml_uint_t HostVMMaxNonCachedPageTableLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1604

dml_uint_t HostVMMinPageSize;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1608

dml_uint_t DynamicMetadataTransmittedBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1612

dml_uint_t PDEAndMetaPTEBytesFrame;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1613

dml_uint_t MetaRowByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1614

dml_uint_t PixelPTEBytesPerRow;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1616

dml_uint_t VInitPreFillY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1617

dml_uint_t MaxNumSwathY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1619

dml_uint_t VInitPreFillC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1620

dml_uint_t MaxNumSwathC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1621

dml_uint_t swath_width_luma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1622

dml_uint_t swath_width_chroma_ub;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1623

dml_uint_t SwathHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1624

dml_uint_t SwathHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1626

dml_uint_t *DSTXAfterScaler;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1627

dml_uint_t *DSTYAfterScaler;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1641

dml_uint_t *VUpdateOffsetPix;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1642

dml_uint_t *VUpdateWidthPix;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1643

dml_uint_t *VReadyOffsetPix;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1648

dml_uint_t dummy_integer[3];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1649

dml_uint_t dummy_integer_array[22][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1652

dml_uint_t MaxVStartupAllPlanes[2];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1653

dml_uint_t MaximumVStartup[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1654

dml_uint_t DSTYAfterScaler[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1655

dml_uint_t DSTXAfterScaler[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1656

dml_uint_t NextPrefetchMode[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1657

dml_uint_t MinPrefetchMode[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1658

dml_uint_t MaxPrefetchMode[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1665

dml_uint_t TotalNumberOfActiveWriteback;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1666

dml_uint_t MaximumSwathWidthSupportLuma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1667

dml_uint_t MaximumSwathWidthSupportChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1671

dml_uint_t NumberOfDPPNoDSC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1675

dml_uint_t NumberOfDPPDSC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1680

dml_uint_t NumberOfNonCombinedSurfaceOfMaximumBandwidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1681

dml_uint_t TotalNumberOfActiveOTG;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1682

dml_uint_t TotalNumberOfActiveHDMIFRL;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1683

dml_uint_t TotalNumberOfActiveDP2p0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1684

dml_uint_t TotalNumberOfActiveDP2p0Outputs;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1685

dml_uint_t TotalSlots;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1686

dml_uint_t DSCFormatFactor;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1687

dml_uint_t TotalDSCUnitsRequired;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1688

dml_uint_t ReorderingBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1697

dml_uint_t NextMaxVStartup;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1698

dml_uint_t MaxVStartup;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1708

dml_uint_t DSCFormatFactor;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1709

dml_uint_t dummy_integer_array[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1712

dml_uint_t dummy_long_array[4][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1716

dml_uint_t ReorderBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1719

dml_uint_t TotalDCCActiveDPP;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1720

dml_uint_t TotalActiveDPP;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1721

dml_uint_t VStartupLines;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1722

dml_uint_t MaxVStartupLines[__DML_NUM_PLANES__]; /// <brief more like vblank for the plane's OTG

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1723

dml_uint_t MaxVStartupAllPlanes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1731

dml_uint_t NextPrefetchMode[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1732

dml_uint_t MinPrefetchMode[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1733

dml_uint_t MaxPrefetchMode[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1761

dml_uint_t LinesInDETYRoundedDownToSwath[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1762

dml_uint_t LinesInDETCRoundedDownToSwath[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1769

dml_uint_t TotalActiveWriteback;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1770

dml_uint_t LBLatencyHidingSourceLinesY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1771

dml_uint_t LBLatencyHidingSourceLinesC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1778

dml_uint_t LastSurfaceWithoutMargin;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1779

dml_uint_t FCLKChangeSupportNumber;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1780

dml_uint_t DRAMClockChangeMethod;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1781

dml_uint_t DRAMClockChangeSupportNumber;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1782

dml_uint_t dst_y_pstate;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1783

dml_uint_t src_y_pstate_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1784

dml_uint_t src_y_pstate_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1785

dml_uint_t src_y_ahead_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1786

dml_uint_t src_y_ahead_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1787

dml_uint_t sub_vp_lines_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1788

dml_uint_t sub_vp_lines_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1792

dml_uint_t PTEBufferSizeInRequestsForLuma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1793

dml_uint_t PTEBufferSizeInRequestsForChroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1794

dml_uint_t PDEAndMetaPTEBytesFrameY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1795

dml_uint_t PDEAndMetaPTEBytesFrameC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1796

dml_uint_t MetaRowByteY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1797

dml_uint_t MetaRowByteC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1798

dml_uint_t PixelPTEBytesPerRowY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1799

dml_uint_t PixelPTEBytesPerRowC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1800

dml_uint_t PixelPTEBytesPerRowStorageY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1801

dml_uint_t PixelPTEBytesPerRowStorageC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1802

dml_uint_t PixelPTEBytesPerRowY_one_row_per_frame[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1803

dml_uint_t PixelPTEBytesPerRowC_one_row_per_frame[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1804

dml_uint_t dpte_row_width_luma_ub_one_row_per_frame[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1805

dml_uint_t dpte_row_height_luma_one_row_per_frame[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1806

dml_uint_t dpte_row_width_chroma_ub_one_row_per_frame[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1807

dml_uint_t dpte_row_height_chroma_one_row_per_frame[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1810

dml_uint_t HostVMDynamicLevels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1814

dml_uint_t dummy1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1815

dml_uint_t dummy2;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1816

dml_uint_t dummy3;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1827

dml_uint_t ExtraLatencyBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1830

dml_uint_t NoOfDPPState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1836

dml_uint_t DPPCycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1837

dml_uint_t DISPCLKCycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1850

dml_uint_t HostVMDynamicLevelsTrips;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1899

dml_uint_t project;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1920

dml_uint_t in_start_state_idx;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1921

dml_uint_t out_lowest_state_idx;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1932

dml_uint_t refcyc_h_blank_end;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1933

dml_uint_t dlg_vblank_end;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1934

dml_uint_t min_dst_y_next_start;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1935

dml_uint_t refcyc_per_htotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1936

dml_uint_t refcyc_x_after_scaler;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1937

dml_uint_t dst_y_after_scaler;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1938

dml_uint_t dst_y_prefetch;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1939

dml_uint_t dst_y_per_vm_vblank;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1940

dml_uint_t dst_y_per_row_vblank;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1941

dml_uint_t dst_y_per_vm_flip;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1942

dml_uint_t dst_y_per_row_flip;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1943

dml_uint_t ref_freq_to_pix_freq;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1944

dml_uint_t vratio_prefetch;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1945

dml_uint_t vratio_prefetch_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1946

dml_uint_t refcyc_per_pte_group_vblank_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1947

dml_uint_t refcyc_per_pte_group_vblank_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1948

dml_uint_t refcyc_per_meta_chunk_vblank_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1949

dml_uint_t refcyc_per_meta_chunk_vblank_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1950

dml_uint_t refcyc_per_pte_group_flip_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1951

dml_uint_t refcyc_per_pte_group_flip_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1952

dml_uint_t refcyc_per_meta_chunk_flip_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1953

dml_uint_t refcyc_per_meta_chunk_flip_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1954

dml_uint_t dst_y_per_pte_row_nom_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1955

dml_uint_t dst_y_per_pte_row_nom_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1956

dml_uint_t refcyc_per_pte_group_nom_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1957

dml_uint_t refcyc_per_pte_group_nom_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1958

dml_uint_t dst_y_per_meta_row_nom_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1959

dml_uint_t dst_y_per_meta_row_nom_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1960

dml_uint_t refcyc_per_meta_chunk_nom_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1961

dml_uint_t refcyc_per_meta_chunk_nom_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1962

dml_uint_t refcyc_per_line_delivery_pre_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1963

dml_uint_t refcyc_per_line_delivery_pre_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1964

dml_uint_t refcyc_per_line_delivery_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1965

dml_uint_t refcyc_per_line_delivery_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1966

dml_uint_t refcyc_per_vm_group_vblank;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1967

dml_uint_t refcyc_per_vm_group_flip;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1968

dml_uint_t refcyc_per_vm_req_vblank;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1969

dml_uint_t refcyc_per_vm_req_flip;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1970

dml_uint_t dst_y_offset_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1971

dml_uint_t chunk_hdl_adjust_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1972

dml_uint_t dst_y_offset_cur1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1973

dml_uint_t chunk_hdl_adjust_cur1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1974

dml_uint_t vready_after_vcount0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1975

dml_uint_t dst_y_delta_drq_limit;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1976

dml_uint_t refcyc_per_vm_dmdata;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1977

dml_uint_t dmdata_dl_delta;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1981

dml_uint_t qos_level_low_wm;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1982

dml_uint_t qos_level_high_wm;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1983

dml_uint_t min_ttu_vblank;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1984

dml_uint_t qos_level_flip;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1985

dml_uint_t refcyc_per_req_delivery_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1986

dml_uint_t refcyc_per_req_delivery_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1987

dml_uint_t refcyc_per_req_delivery_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1988

dml_uint_t refcyc_per_req_delivery_cur1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1989

dml_uint_t refcyc_per_req_delivery_pre_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1990

dml_uint_t refcyc_per_req_delivery_pre_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1991

dml_uint_t refcyc_per_req_delivery_pre_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1992

dml_uint_t refcyc_per_req_delivery_pre_cur1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1993

dml_uint_t qos_level_fixed_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1994

dml_uint_t qos_level_fixed_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1995

dml_uint_t qos_level_fixed_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1996

dml_uint_t qos_level_fixed_cur1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1997

dml_uint_t qos_ramp_disable_l;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1998

dml_uint_t qos_ramp_disable_c;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

1999

dml_uint_t qos_ramp_disable_cur0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2000

dml_uint_t qos_ramp_disable_cur1;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2004

dml_uint_t max_req_outstanding;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2005

dml_uint_t min_req_outstanding;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2006

dml_uint_t sat_level_us;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2007

dml_uint_t hvm_max_qos_commit_threshold;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2008

dml_uint_t hvm_min_req_outstand_commit_threshold;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2009

dml_uint_t compbuf_reserved_space_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2013

dml_uint_t chunk_size;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2014

dml_uint_t min_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2015

dml_uint_t meta_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2016

dml_uint_t min_meta_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2017

dml_uint_t dpte_group_size;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2018

dml_uint_t mpte_group_size;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2019

dml_uint_t swath_height;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2020

dml_uint_t pte_row_height_linear;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2026

dml_uint_t drq_expansion_mode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2027

dml_uint_t prq_expansion_mode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2028

dml_uint_t mrq_expansion_mode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2029

dml_uint_t crq_expansion_mode;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

2030

dml_uint_t plane1_base_address;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

307

dml_uint_t urgent_ramp_uclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

308

dml_uint_t trip_to_memory_uclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

309

dml_uint_t meta_trip_to_memory_uclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

310

dml_uint_t maximum_latency_when_urgent_uclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

311

dml_uint_t average_latency_when_urgent_uclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

312

dml_uint_t maximum_latency_when_non_urgent_uclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

313

dml_uint_t average_latency_when_non_urgent_uclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

323

dml_uint_t max_outstanding_reqs;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

344

dml_uint_t round_trip_ping_latency_dcfclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

345

dml_uint_t urgent_out_of_order_return_per_channel_pixel_only_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

346

dml_uint_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

347

dml_uint_t urgent_out_of_order_return_per_channel_vm_only_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

348

dml_uint_t num_chans;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

349

dml_uint_t return_bus_width_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

350

dml_uint_t dram_channel_width_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

351

dml_uint_t fabric_datapath_to_dcn_data_return_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

352

dml_uint_t hostvm_min_page_size_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

353

dml_uint_t gpuvm_min_page_size_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

357

dml_uint_t mall_allocated_for_dcn_mbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

361

dml_uint_t mem_word_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

362

dml_uint_t num_dcc_mcaches;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

363

dml_uint_t mcache_size_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

364

dml_uint_t mcache_line_size_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

368

dml_uint_t df_qos_response_time_fclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

369

dml_uint_t max_round_trip_to_furthest_cs_fclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

370

dml_uint_t mall_overhead_fclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

371

dml_uint_t meta_trip_adder_fclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

372

dml_uint_t average_transport_distance_fclk_cycles;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

383

dml_uint_t vblank_nom_default_us;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

384

dml_uint_t rob_buffer_size_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

385

dml_uint_t config_return_buffer_size_in_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

386

dml_uint_t config_return_buffer_segment_size_in_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

387

dml_uint_t compressed_buffer_segment_size_in_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

388

dml_uint_t meta_fifo_size_in_kentries;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

389

dml_uint_t zero_size_buffer_entries;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

390

dml_uint_t dpte_buffer_size_in_pte_reqs_luma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

391

dml_uint_t dpte_buffer_size_in_pte_reqs_chroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

392

dml_uint_t dcc_meta_buffer_size_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

395

dml_uint_t gpuvm_max_page_table_levels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

396

dml_uint_t hostvm_max_page_table_levels;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

397

dml_uint_t pixel_chunk_size_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

398

dml_uint_t alpha_pixel_chunk_size_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

399

dml_uint_t min_pixel_chunk_size_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

400

dml_uint_t meta_chunk_size_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

401

dml_uint_t min_meta_chunk_size_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

402

dml_uint_t writeback_chunk_size_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

403

dml_uint_t line_buffer_size_bits;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

404

dml_uint_t max_line_buffer_lines;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

405

dml_uint_t writeback_interface_buffer_size_kbytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

406

dml_uint_t max_num_dpp;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

407

dml_uint_t max_num_otg;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

408

dml_uint_t max_num_wb;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

409

dml_uint_t max_dchub_pscl_bw_pix_per_clk;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

410

dml_uint_t max_pscl_lb_bw_pix_per_clk;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

411

dml_uint_t max_lb_vscl_bw_pix_per_clk;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

412

dml_uint_t max_vscl_hscl_bw_pix_per_clk;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

415

dml_uint_t max_hscl_taps;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

416

dml_uint_t max_vscl_taps;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

417

dml_uint_t num_dsc;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

418

dml_uint_t maximum_dsc_bits_per_component;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

419

dml_uint_t maximum_pixels_per_line_per_dsc_unit;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

423

dml_uint_t dppclk_delay_subtotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

424

dml_uint_t dppclk_delay_scl;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

425

dml_uint_t dppclk_delay_scl_lb_only;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

426

dml_uint_t dppclk_delay_cnvc_formatter;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

427

dml_uint_t dppclk_delay_cnvc_cursor;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

428

dml_uint_t cursor_buffer_size;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

429

dml_uint_t cursor_chunk_size;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

430

dml_uint_t dispclk_delay_subtotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

432

dml_uint_t max_inter_dcn_tile_repeaters;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

433

dml_uint_t max_num_hdmi_frl_outputs;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

434

dml_uint_t max_num_dp2p0_outputs;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

435

dml_uint_t max_num_dp2p0_streams;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

442

dml_uint_t writeback_max_hscl_taps;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

443

dml_uint_t writeback_max_vscl_taps;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

444

dml_uint_t writeback_line_buffer_buffer_size;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

452

dml_uint_t DPPPerSurface;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

455

dml_uint_t ViewportHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

456

dml_uint_t ViewportHeightChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

457

dml_uint_t BlockWidth256BytesY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

458

dml_uint_t BlockHeight256BytesY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

459

dml_uint_t BlockWidth256BytesC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

460

dml_uint_t BlockHeight256BytesC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

461

dml_uint_t BlockWidthY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

462

dml_uint_t BlockHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

463

dml_uint_t BlockWidthC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

464

dml_uint_t BlockHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

465

dml_uint_t InterlaceEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

466

dml_uint_t NumberOfCursors;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

467

dml_uint_t VBlank;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

468

dml_uint_t HTotal;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

469

dml_uint_t HActive;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

474

dml_uint_t BytePerPixelY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

475

dml_uint_t BytePerPixelC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

479

dml_uint_t VTaps;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

480

dml_uint_t VTapsChroma;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

481

dml_uint_t PitchY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

482

dml_uint_t DCCMetaPitchY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

483

dml_uint_t PitchC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

484

dml_uint_t DCCMetaPitchC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

486

dml_uint_t ViewportXStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

487

dml_uint_t ViewportYStart;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

488

dml_uint_t ViewportXStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

489

dml_uint_t ViewportYStartC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

491

dml_uint_t SwathHeightY;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

492

dml_uint_t SwathHeightC;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

531

dml_uint_t GPUVMMaxPageTableLevels; /// <brief GPUVM level; max of all pipes'

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

532

dml_uint_t HostVMMaxPageTableLevels; /// <brief HostVM level; max of all pipes'; that is the number of non-cache HVM level

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

534

dml_uint_t GPUVMMinPageSizeKBytes[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

538

dml_uint_t ViewportWidth[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

539

dml_uint_t ViewportHeight[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

540

dml_uint_t ViewportWidthChroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

541

dml_uint_t ViewportHeightChroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

542

dml_uint_t ViewportXStart[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

543

dml_uint_t ViewportXStartC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

544

dml_uint_t ViewportYStart[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

545

dml_uint_t ViewportYStartC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

553

dml_uint_t HTaps[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

554

dml_uint_t VTaps[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

555

dml_uint_t HTapsChroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

556

dml_uint_t VTapsChroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

557

dml_uint_t LBBitPerPixel[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

560

dml_uint_t ScalerRecoutWidth[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

563

dml_uint_t DynamicMetadataLinesBeforeActiveRequired[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

564

dml_uint_t DynamicMetadataTransmittedBytes[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

565

dml_uint_t DETSizeOverride[__DML_NUM_PLANES__]; /// <brief user can specify the desire DET buffer usage per-plane

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

567

dml_uint_t NumberOfCursors[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

568

dml_uint_t CursorWidth[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

569

dml_uint_t CursorBPP[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

578

dml_uint_t BlendingAndTiming[__DML_NUM_PLANES__]; /// <brief From which timing group (like OTG) that this plane is getting its timing from. Mode check also need this info for example to check num OTG; encoder; dsc etc.

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

585

dml_uint_t PitchY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

586

dml_uint_t SurfaceWidthY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

587

dml_uint_t SurfaceHeightY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

588

dml_uint_t PitchC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

589

dml_uint_t SurfaceWidthC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

590

dml_uint_t SurfaceHeightC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

593

dml_uint_t DCCMetaPitchY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

594

dml_uint_t DCCMetaPitchC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

604

dml_uint_t HTotal[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

605

dml_uint_t VTotal[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

606

dml_uint_t HBlankEnd[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

607

dml_uint_t VBlankEnd[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

608

dml_uint_t RefreshRate[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

609

dml_uint_t VFrontPorch[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

611

dml_uint_t HActive[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

612

dml_uint_t VActive[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

615

dml_uint_t VBlankNom[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

621

dml_uint_t DSCInputBitPerComponent[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

624

dml_uint_t OutputMultistreamId[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

629

dml_uint_t OutputLinkDPLanes[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

632

dml_uint_t AudioSampleRate[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

633

dml_uint_t AudioSampleLayout[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

635

dml_uint_t DSCSlices[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

642

dml_uint_t ActiveWritebacksPerSurface[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

643

dml_uint_t WritebackDestinationWidth[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

644

dml_uint_t WritebackDestinationHeight[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

645

dml_uint_t WritebackSourceWidth[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

646

dml_uint_t WritebackSourceHeight[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

647

dml_uint_t WritebackHTaps[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

648

dml_uint_t WritebackVTaps[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

658

dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

660

dml_uint_t NumberOfDSCSlices[__DML_NUM_PLANES__]; /// <brief Indicate how many slices needed to support the given mode

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

711

dml_uint_t NomDETInKByteOverrideValue;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

727

dml_uint_t MaximumMPCCombine; //<brief If using MPC combine helps the power saving support; then this will be set to 1

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

729

dml_uint_t CompressedBufferSizeInkByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

776

dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

794

dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

797

dml_uint_t NumberOfDSCSlices[__DML_NUM_PLANES__]; /// <brief Indicate how many slices needed to support the given mode

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

817

dml_uint_t state_idx; //<brief The power state idx for the power state under this computation

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

818

dml_uint_t max_state_idx; //<brief The MAX power state idx

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

823

dml_uint_t num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

845

dml_uint_t MaxTotalDETInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

846

dml_uint_t NomDETInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

847

dml_uint_t MinCompressedBufferSizeInKByte;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

853

dml_uint_t DETBufferSizeInKByte[__DML_NUM_PLANES__]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

854

dml_uint_t DETBufferSizeY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

855

dml_uint_t DETBufferSizeC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

856

dml_uint_t SwathHeightY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

857

dml_uint_t SwathHeightC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

862

dml_uint_t TotImmediateFlipBytes;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

868

dml_uint_t SwathWidthYAllStates[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

869

dml_uint_t SwathWidthCAllStates[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

870

dml_uint_t SwathHeightYAllStates[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

871

dml_uint_t SwathHeightCAllStates[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

872

dml_uint_t SwathWidthYThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

873

dml_uint_t SwathWidthCThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

874

dml_uint_t SwathHeightYThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

875

dml_uint_t SwathHeightCThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

876

dml_uint_t DETBufferSizeInKByteAllStates[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

877

dml_uint_t DETBufferSizeYAllStates[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

878

dml_uint_t DETBufferSizeCAllStates[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

880

dml_uint_t CompressedBufferSizeInkByteAllStates[2];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

882

dml_uint_t CompressedBufferSizeInkByteThisState;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

883

dml_uint_t DETBufferSizeInKByteThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

884

dml_uint_t DETBufferSizeYThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

885

dml_uint_t DETBufferSizeCThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

888

dml_uint_t swath_width_luma_ub_all_states[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

889

dml_uint_t swath_width_chroma_ub_all_states[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

890

dml_uint_t swath_width_luma_ub_this_state[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

891

dml_uint_t swath_width_chroma_ub_this_state[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

892

dml_uint_t RequiredSlots[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

893

dml_uint_t PDEAndMetaPTEBytesPerFrame[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

894

dml_uint_t MetaRowBytes[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

895

dml_uint_t DPTEBytesPerRow[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

896

dml_uint_t PrefetchLinesY[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

897

dml_uint_t PrefetchLinesC[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

898

dml_uint_t MaxNumSwY[__DML_NUM_PLANES__]; /// <brief Max number of swath for prefetch

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

899

dml_uint_t MaxNumSwC[__DML_NUM_PLANES__]; /// <brief Max number of swath for prefetch

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

900

dml_uint_t PrefillY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

901

dml_uint_t PrefillC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

903

dml_uint_t PrefetchLinesYThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

904

dml_uint_t PrefetchLinesCThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

905

dml_uint_t DPTEBytesPerRowThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

906

dml_uint_t PDEAndMetaPTEBytesPerFrameThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

907

dml_uint_t MetaRowBytesThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

918

dml_uint_t BytePerPixelY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

919

dml_uint_t BytePerPixelC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

923

dml_uint_t Read256BlockHeightY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

924

dml_uint_t Read256BlockWidthY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

925

dml_uint_t Read256BlockHeightC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

926

dml_uint_t Read256BlockWidthC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

927

dml_uint_t MacroTileHeightY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

928

dml_uint_t MacroTileHeightC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

929

dml_uint_t MacroTileWidthY[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

930

dml_uint_t MacroTileWidthC[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

939

dml_uint_t dpte_group_bytes[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

940

dml_uint_t dpte_row_height[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

941

dml_uint_t dpte_row_height_chroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

942

dml_uint_t meta_row_height[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

943

dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

959

dml_uint_t DSCDelayPerState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

984

dml_uint_t SurfaceSizeInMALL[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

985

dml_uint_t NoOfDPP[2][__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

986

dml_uint_t NoOfDPPThisState[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

997

dml_uint_t PrefetchMode[__DML_NUM_PLANES__];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

998

dml_uint_t TotalNumberOfActiveDPP[2];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

999

dml_uint_t TotalNumberOfSingleDPPSurfaces[2];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

201

dml_uint_t dml_round_to_multiple(dml_uint_t num, dml_uint_t multiple, dml_bool_t up)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

203

dml_uint_t remainder;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

345

for (dml_uint_t i = 0; i < DCN_DML__NUM_PLANE; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

354

void dml_print_mode_support(struct display_mode_lib_st *mode_lib, dml_uint_t j)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

491

for (dml_uint_t j = 0; j < 2; j++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

527

void dml_print_dml_display_cfg_timing(const struct dml_timing_cfg_st *timing, dml_uint_t num_plane)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

529

for (dml_uint_t i = 0; i < num_plane; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

543

void dml_print_dml_display_cfg_plane(const struct dml_plane_cfg_st *plane, dml_uint_t num_plane)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

551

for (dml_uint_t i = 0; i < num_plane; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

591

void dml_print_dml_display_cfg_surface(const struct dml_surface_cfg_st *surface, dml_uint_t num_plane)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

593

for (dml_uint_t i = 0; i < num_plane; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

610

void dml_print_dml_display_cfg_hw_resource(const struct dml_hw_resource_st *hw, dml_uint_t num_plane)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

612

for (dml_uint_t i = 0; i < num_plane; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

696

for (dml_uint_t i = 0; i < DCN_DML__NUM_PLANE; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

713

dml_uint_t dml_get_cursor_bit_per_pixel(enum dml_cursor_bpp ebpp)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

728

dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

730

dml_uint_t num_active_planes = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

732

for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; k++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

743

dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

745

dml_uint_t num_active_pipes = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

747

for (dml_uint_t j = 0; j < dml_get_num_active_planes(display_cfg); j++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

757

dml_uint_t dml_get_plane_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

759

dml_uint_t plane_idx = mode_lib->mp.pipe_plane[pipe_idx];

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

763

dml_uint_t dml_get_pipe_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t plane_idx)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

765

dml_uint_t pipe_idx = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

770

for (dml_uint_t i = 0; i < __DML_NUM_PLANES__; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

782

void dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

784

dml_uint_t pipe_idx = 0;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

786

for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

790

for (dml_uint_t plane_idx = 0; plane_idx < __DML_NUM_PLANES__; plane_idx++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

791

for (dml_uint_t i = 0; i < hw->DPPPerSurface[plane_idx]; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

51

__DML_DLL_EXPORT__ dml_uint_t dml_round_to_multiple(dml_uint_t num, dml_uint_t multiple, dml_bool_t up);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

53

__DML_DLL_EXPORT__ dml_uint_t dml_get_cursor_bit_per_pixel(enum dml_cursor_bpp ebpp);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

59

__DML_DLL_EXPORT__ void dml_print_mode_support(struct display_mode_lib_st *mode_lib, dml_uint_t j);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

61

__DML_DLL_EXPORT__ void dml_print_dml_display_cfg_timing(const struct dml_timing_cfg_st *timing, dml_uint_t num_plane);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

62

__DML_DLL_EXPORT__ void dml_print_dml_display_cfg_plane(const struct dml_plane_cfg_st *plane, dml_uint_t num_plane);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

63

__DML_DLL_EXPORT__ void dml_print_dml_display_cfg_surface(const struct dml_surface_cfg_st *surface, dml_uint_t num_plane);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

64

__DML_DLL_EXPORT__ void dml_print_dml_display_cfg_hw_resource(const struct dml_hw_resource_st *hw, dml_uint_t num_plane);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

69

__DML_DLL_EXPORT__ dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

70

__DML_DLL_EXPORT__ dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

71

__DML_DLL_EXPORT__ dml_uint_t dml_get_plane_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

72

__DML_DLL_EXPORT__ dml_uint_t dml_get_pipe_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t plane_idx);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

73

__DML_DLL_EXPORT__ void dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane);

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1007

dml_uint_t width, height;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

685

out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

686

out->fabric_datapath_to_dcn_data_return_bytes = (dml_uint_t)in_soc_params->fabric_datapath_to_dcn_data_return_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

689

out->mall_allocated_for_dcn_mbytes = (dml_uint_t)in_soc_params->mall_allocated_for_dcn_mbytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

754

dml_uint_t hblank_start, vblank_start;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

240

static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx)

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

103

rq_regs->rq_regs_l.min_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) min_pixel_chunk_bytes) - 8 + 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

108

rq_regs->rq_regs_c.min_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_min_pixel_chunk_bytes) - 8 + 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

110

rq_regs->rq_regs_l.meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) meta_chunk_bytes) - 10);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

111

rq_regs->rq_regs_c.meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_meta_chunk_bytes) - 10);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

116

rq_regs->rq_regs_l.min_meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) min_meta_chunk_bytes) - 6 + 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

121

rq_regs->rq_regs_c.min_meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_min_meta_chunk_bytes) - 6 + 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

123

rq_regs->rq_regs_l.dpte_group_size = (dml_uint_t)(dml_log2((dml_float_t) dpte_group_bytes) - 6);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

124

rq_regs->rq_regs_l.mpte_group_size = (dml_uint_t)(dml_log2((dml_float_t) mpte_group_bytes) - 6);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

125

rq_regs->rq_regs_c.dpte_group_size = (dml_uint_t)(dml_log2((dml_float_t) p1_dpte_group_bytes) - 6);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

126

rq_regs->rq_regs_c.mpte_group_size = (dml_uint_t)(dml_log2((dml_float_t) p1_mpte_group_bytes) - 6);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

128

detile_buf_size_in_bytes = (dml_uint_t)(dml_get_det_buffer_size_kbytes(mode_lib, pipe_idx) * 1024);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

130

pte_row_height_linear = (dml_uint_t)(dml_get_dpte_row_height_linear_l(mode_lib, pipe_idx));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

135

rq_regs->rq_regs_l.pte_row_height_linear = (dml_uint_t)(dml_floor(dml_log2((dml_float_t) pte_row_height_linear), 1) - 3);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

138

dml_uint_t p1_pte_row_height_linear = (dml_uint_t)(dml_get_dpte_row_height_linear_c(mode_lib, pipe_idx));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

142

rq_regs->rq_regs_c.pte_row_height_linear = (dml_uint_t)(dml_floor(dml_log2((dml_float_t) p1_pte_row_height_linear), 1) - 3);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

145

rq_regs->rq_regs_l.swath_height = (dml_uint_t)(dml_log2((dml_float_t) dml_get_swath_height_l(mode_lib, pipe_idx)));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

146

rq_regs->rq_regs_c.swath_height = (dml_uint_t)(dml_log2((dml_float_t) dml_get_swath_height_c(mode_lib, pipe_idx)));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

164

detile_buf_plane1_addr = (dml_uint_t)((1024.0*1024.0) / 2.0 / 1024.0); // half to chroma

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

167

detile_buf_plane1_addr = (dml_uint_t)(detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

172

detile_buf_plane1_addr = (dml_uint_t)(dml_round_to_multiple((dml_uint_t)((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0); // 2/3 to luma

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

200

const dml_uint_t pipe_idx)

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

202

dml_uint_t plane_idx = dml_get_plane_idx(mode_lib, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

208

dml_uint_t num_cursors = plane->NumberOfCursors[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

211

dml_uint_t htotal = timing->HTotal[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

212

dml_uint_t hactive = timing->HActive[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

213

dml_uint_t hblank_end = timing->HBlankEnd[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

214

dml_uint_t vblank_end = timing->VBlankEnd[plane_idx];

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

220

dml_uint_t vready_after_vcount0;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

222

dml_uint_t dst_x_after_scaler;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

223

dml_uint_t dst_y_after_scaler;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

267

dml_uint_t min_dst_y_next_start;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

290

disp_dlg_regs->refcyc_h_blank_end = (dml_uint_t)((dml_float_t) hblank_end * ref_freq_to_pix_freq);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

293

dml_uint_t num_active_pipes = dml_get_num_active_pipes(&mode_lib->ms.cache_display_cfg);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

294

dml_uint_t first_pipe_idx_in_plane = __DML_NUM_PLANES__;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

295

dml_uint_t pipe_idx_in_combine = 0; // pipe index within the plane

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

296

dml_uint_t odm_combine_factor = (odm_mode == dml_odm_mode_combine_2to1 ? 2 : 4);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

298

for (dml_uint_t i = 0; i < num_active_pipes; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

307

disp_dlg_regs->refcyc_h_blank_end = (dml_uint_t)(((dml_float_t) hblank_end + (dml_float_t) pipe_idx_in_combine * (dml_float_t) hactive / (dml_float_t) odm_combine_factor) * ref_freq_to_pix_freq);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

315

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (dml_uint_t)dml_pow(2, 13));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

317

disp_dlg_regs->ref_freq_to_pix_freq = (dml_uint_t)(ref_freq_to_pix_freq * dml_pow(2, 19));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

319

disp_dlg_regs->refcyc_per_htotal = (dml_uint_t)(ref_freq_to_pix_freq * (dml_float_t)htotal * temp);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

323

min_dst_y_next_start = (dml_uint_t)(dml_get_min_dst_y_next_start(mode_lib, pipe_idx));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

329

vready_after_vcount0 = (dml_uint_t)(dml_get_vready_at_or_after_vsync(mode_lib, pipe_idx));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

334

dst_x_after_scaler = (dml_uint_t)(dml_get_dst_x_after_scaler(mode_lib, pipe_idx));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

335

dst_y_after_scaler = (dml_uint_t)(dml_get_dst_y_after_scaler(mode_lib, pipe_idx));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

383

disp_dlg_regs->refcyc_per_vm_dmdata = (dml_uint_t)(dml_get_refcyc_per_vm_dmdata_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

384

disp_dlg_regs->dmdata_dl_delta = (dml_uint_t)(dml_get_dmdata_dl_delta_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

41

const dml_uint_t pipe_idx)

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

411

disp_dlg_regs->min_dst_y_next_start = (dml_uint_t)((dml_float_t) min_dst_y_next_start * dml_pow(2, 2));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

412

ASSERT(disp_dlg_regs->min_dst_y_next_start < (dml_uint_t)dml_pow(2, 18));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

415

disp_dlg_regs->refcyc_x_after_scaler = (dml_uint_t)((dml_float_t) dst_x_after_scaler * ref_freq_to_pix_freq); // in terms of refclk

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

416

disp_dlg_regs->dst_y_prefetch = (dml_uint_t)(dst_y_prefetch * dml_pow(2, 2));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

417

disp_dlg_regs->dst_y_per_vm_vblank = (dml_uint_t)(dst_y_per_vm_vblank * dml_pow(2, 2));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

418

disp_dlg_regs->dst_y_per_row_vblank = (dml_uint_t)(dst_y_per_row_vblank * dml_pow(2, 2));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

419

disp_dlg_regs->dst_y_per_vm_flip = (dml_uint_t)(dst_y_per_vm_flip * dml_pow(2, 2));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

420

disp_dlg_regs->dst_y_per_row_flip = (dml_uint_t)(dst_y_per_row_flip * dml_pow(2, 2));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

422

disp_dlg_regs->vratio_prefetch = (dml_uint_t)(vratio_pre_l * dml_pow(2, 19));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

423

disp_dlg_regs->vratio_prefetch_c = (dml_uint_t)(vratio_pre_c * dml_pow(2, 19));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

43

dml_uint_t plane_idx = dml_get_plane_idx(mode_lib, pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

430

disp_dlg_regs->refcyc_per_vm_group_vblank = (dml_uint_t)(dml_get_refcyc_per_vm_group_vblank_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

431

disp_dlg_regs->refcyc_per_vm_group_flip = (dml_uint_t)(dml_get_refcyc_per_vm_group_flip_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

432

disp_dlg_regs->refcyc_per_vm_req_vblank = (dml_uint_t)(dml_get_refcyc_per_vm_req_vblank_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

433

disp_dlg_regs->refcyc_per_vm_req_flip = (dml_uint_t)(dml_get_refcyc_per_vm_req_flip_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

454

disp_dlg_regs->dst_y_per_pte_row_nom_l = (dml_uint_t)(dst_y_per_pte_row_nom_l * dml_pow(2, 2));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

455

disp_dlg_regs->dst_y_per_pte_row_nom_c = (dml_uint_t)(dst_y_per_pte_row_nom_c * dml_pow(2, 2));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

456

disp_dlg_regs->dst_y_per_meta_row_nom_l = (dml_uint_t)(dst_y_per_meta_row_nom_l * dml_pow(2, 2));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

457

disp_dlg_regs->dst_y_per_meta_row_nom_c = (dml_uint_t)(dst_y_per_meta_row_nom_c * dml_pow(2, 2));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

458

disp_dlg_regs->refcyc_per_pte_group_nom_l = (dml_uint_t)(refcyc_per_pte_group_nom_l);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

459

disp_dlg_regs->refcyc_per_pte_group_nom_c = (dml_uint_t)(refcyc_per_pte_group_nom_c);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

460

disp_dlg_regs->refcyc_per_pte_group_vblank_l = (dml_uint_t)(refcyc_per_pte_group_vblank_l);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

461

disp_dlg_regs->refcyc_per_pte_group_vblank_c = (dml_uint_t)(refcyc_per_pte_group_vblank_c);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

462

disp_dlg_regs->refcyc_per_pte_group_flip_l = (dml_uint_t)(refcyc_per_pte_group_flip_l);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

463

disp_dlg_regs->refcyc_per_pte_group_flip_c = (dml_uint_t)(refcyc_per_pte_group_flip_c);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

464

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (dml_uint_t)(refcyc_per_meta_chunk_nom_l);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

465

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (dml_uint_t)(refcyc_per_meta_chunk_nom_c);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

466

disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (dml_uint_t)(refcyc_per_meta_chunk_vblank_l);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

467

disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = (dml_uint_t)(refcyc_per_meta_chunk_vblank_c);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

468

disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (dml_uint_t)(refcyc_per_meta_chunk_flip_l);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

469

disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (dml_uint_t)(refcyc_per_meta_chunk_flip_c);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

470

disp_dlg_regs->refcyc_per_line_delivery_pre_l = (dml_uint_t)dml_floor(refcyc_per_line_delivery_pre_l, 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

471

disp_dlg_regs->refcyc_per_line_delivery_l = (dml_uint_t)dml_floor(refcyc_per_line_delivery_l, 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

472

disp_dlg_regs->refcyc_per_line_delivery_pre_c = (dml_uint_t)dml_floor(refcyc_per_line_delivery_pre_c, 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

473

disp_dlg_regs->refcyc_per_line_delivery_c = (dml_uint_t)dml_floor(refcyc_per_line_delivery_c, 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

482

disp_ttu_regs->refcyc_per_req_delivery_pre_l = (dml_uint_t)(refcyc_per_req_delivery_pre_l * dml_pow(2, 10));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

483

disp_ttu_regs->refcyc_per_req_delivery_l = (dml_uint_t)(refcyc_per_req_delivery_l * dml_pow(2, 10));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

484

disp_ttu_regs->refcyc_per_req_delivery_pre_c = (dml_uint_t)(refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

485

disp_ttu_regs->refcyc_per_req_delivery_c = (dml_uint_t)(refcyc_per_req_delivery_c * dml_pow(2, 10));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

486

disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (dml_uint_t)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

487

disp_ttu_regs->refcyc_per_req_delivery_cur0 = (dml_uint_t)(refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

492

disp_ttu_regs->qos_level_high_wm = (dml_uint_t)(4.0 * (dml_float_t)htotal * ref_freq_to_pix_freq);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

501

disp_ttu_regs->min_ttu_vblank = (dml_uint_t)(min_ttu_vblank * refclk_freq_in_mhz);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

508

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (dml_uint_t)dml_pow(2, 23))

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

509

disp_dlg_regs->refcyc_per_vm_group_vblank = (dml_uint_t)(dml_pow(2, 23) - 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

511

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (dml_uint_t)dml_pow(2, 23))

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

512

disp_dlg_regs->refcyc_per_vm_group_flip = (dml_uint_t)(dml_pow(2, 23) - 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

514

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (dml_uint_t)dml_pow(2, 23))

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

515

disp_dlg_regs->refcyc_per_vm_req_vblank = (dml_uint_t)(dml_pow(2, 23) - 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

517

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (dml_uint_t)dml_pow(2, 23))

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

518

disp_dlg_regs->refcyc_per_vm_req_flip = (dml_uint_t)(dml_pow(2, 23) - 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

521

ASSERT(disp_dlg_regs->dst_y_after_scaler < (dml_uint_t)8);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

522

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (dml_uint_t)dml_pow(2, 13));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

523

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (dml_uint_t)dml_pow(2, 17));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

525

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (dml_uint_t)dml_pow(2, 17)) { // FIXME what so special about chroma, can we just assert?

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

526

dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u > register max U15.2 %u\n", __func__, disp_dlg_regs->dst_y_per_pte_row_nom_c, (dml_uint_t)dml_pow(2, 17) - 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

529

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (dml_uint_t)dml_pow(2, 17));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

530

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (dml_uint_t)dml_pow(2, 17));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

532

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (dml_uint_t)dml_pow(2, 23))

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

533

disp_dlg_regs->refcyc_per_pte_group_nom_l = (dml_uint_t)(dml_pow(2, 23) - 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

535

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (dml_uint_t)dml_pow(2, 23))

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

536

disp_dlg_regs->refcyc_per_pte_group_nom_c = (dml_uint_t)(dml_pow(2, 23) - 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

538

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (dml_uint_t)dml_pow(2, 13));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

540

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (dml_uint_t)dml_pow(2, 13));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

543

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (dml_uint_t)dml_pow(2, 23))

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

544

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (dml_uint_t)(dml_pow(2, 23) - 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

546

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (dml_uint_t)dml_pow(2, 23))

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

547

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (dml_uint_t)(dml_pow(2, 23) - 1);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

549

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (dml_uint_t)dml_pow(2, 13));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

550

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_c < (dml_uint_t)dml_pow(2, 13));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

551

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (dml_uint_t)dml_pow(2, 13));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

552

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (dml_uint_t)dml_pow(2, 13));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

553

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (dml_uint_t)dml_pow(2, 13));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

554

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (dml_uint_t)dml_pow(2, 13));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

555

ASSERT(disp_ttu_regs->qos_level_low_wm < (dml_uint_t) dml_pow(2, 14));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

556

ASSERT(disp_ttu_regs->qos_level_high_wm < (dml_uint_t) dml_pow(2, 14));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

557

ASSERT(disp_ttu_regs->min_ttu_vblank < (dml_uint_t) dml_pow(2, 24));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

62

dml_uint_t detile_buf_size_in_bytes;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

63

dml_uint_t detile_buf_plane1_addr = 0;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

69

dml_uint_t pte_row_height_linear;

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

75

pixel_chunk_bytes = (dml_uint_t)(dml_get_pixel_chunk_size_in_kbyte(mode_lib) * 1024);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

76

min_pixel_chunk_bytes = (dml_uint_t)(dml_get_min_pixel_chunk_size_in_byte(mode_lib));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

81

meta_chunk_bytes = (dml_uint_t)(dml_get_meta_chunk_size_in_kbyte(mode_lib) * 1024);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

82

min_meta_chunk_bytes = (dml_uint_t)(dml_get_min_meta_chunk_size_in_byte(mode_lib));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

84

dpte_group_bytes = (dml_uint_t)(dml_get_dpte_group_size_in_bytes(mode_lib, pipe_idx));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

85

mpte_group_bytes = (dml_uint_t)(dml_get_vm_group_size_in_bytes(mode_lib, pipe_idx));

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

95

p1_pixel_chunk_bytes = (dml_uint_t)(dml_get_alpha_pixel_chunk_size_in_kbyte(mode_lib) * 1024);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

97

rq_regs->rq_regs_l.chunk_size = (dml_uint_t)(dml_log2((dml_float_t) pixel_chunk_bytes) - 10);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c

98

rq_regs->rq_regs_c.chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_pixel_chunk_bytes) - 10);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.h

45

const dml_uint_t pipe_idx);

sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.h

58

const dml_uint_t pipe_idx);