Symbol: dml_min
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1037
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1042
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1061
*dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1116
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1125
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1134
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1157
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1167
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1176
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1302
mode_lib->vba.ReturnBandwidthToDCN = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1315
mode_lib->vba.ReturnBandwidthToDCN = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1344
mode_lib->vba.SwathWidthY[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1615
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1646
mode_lib->vba.SmallestVBlank = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1709
+ dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1732
+ dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1752
mode_lib->vba.UrgentLatencySupportUs[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1763
mode_lib->vba.MinUrgentLatencySupportUs = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2111
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2157
mode_lib->vba.VStartup[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2167
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
237
mode_lib->vba.FabricAndDRAMBandwidth = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2410
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2422
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2510
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2534
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2548
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2559
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
257
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2698
VStartupMargin = dml_min(VStartupMargin, Margin);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
280
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2860
SwathWidth = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3174
min_row_time = dml_min(dpte_row_height, meta_row_height) * LineTime
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3439
locals->FabricAndDRAMBandwidthPerState[i] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3444
locals->ReturnBWToDCNPerState = dml_min(locals->ReturnBusWidth * locals->DCFCLKPerState[i],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3451
locals->ReturnBWPerState[i][0] = dml_min(locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3462
locals->ReturnBWPerState[i][0] = dml_min(locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3470
locals->ReturnBWToDCNPerState = dml_min(locals->ReturnBusWidth *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3474
locals->ReturnBWPerState[i][0] = dml_min(locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3485
locals->ReturnBWPerState[i][0] = dml_min(locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3508
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3667
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3676
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3686
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3702
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3712
locals->PSCL_FACTOR_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3720
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3728
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3817
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3839
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3867
locals->MaximumSwathWidth[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4003
if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4057
dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4301
locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4342
locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4346
locals->EffectiveLBLatencyHidingSourceLinesChroma = dml_min(locals->MaxLineBufferLines,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4351
locals->EffectiveDETLBLinesLuma = dml_floor(locals->LinesInDETLuma + dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4358
dml_min(locals->LinesInDETChroma * locals->RequiredDISPCLK[i][j] *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4372
locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4931
mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][0] = dml_min(mode_lib->vba.ReturnBusWidth *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1097
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1102
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1121
*dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1176
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1185
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1194
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1217
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1227
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1236
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1362
mode_lib->vba.ReturnBandwidthToDCN = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1375
mode_lib->vba.ReturnBandwidthToDCN = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1404
mode_lib->vba.SwathWidthY[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1651
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1682
mode_lib->vba.SmallestVBlank = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1745
+ dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1768
+ dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1788
mode_lib->vba.UrgentLatencySupportUs[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1799
mode_lib->vba.MinUrgentLatencySupportUs = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2145
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2191
mode_lib->vba.VStartup[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2201
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2444
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2456
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2544
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2568
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2582
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2593
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
261
mode_lib->vba.FabricAndDRAMBandwidth = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2771
VStartupMargin = dml_min(VStartupMargin, Margin);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
281
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2933
SwathWidth = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
304
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3247
min_row_time = dml_min(dpte_row_height, meta_row_height) * LineTime
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3546
locals->FabricAndDRAMBandwidthPerState[i] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3551
locals->ReturnBWToDCNPerState = dml_min(locals->ReturnBusWidth * locals->DCFCLKPerState[i],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3558
locals->ReturnBWPerState[i][0] = dml_min(locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3569
locals->ReturnBWPerState[i][0] = dml_min(locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3577
locals->ReturnBWToDCNPerState = dml_min(locals->ReturnBusWidth *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3581
locals->ReturnBWPerState[i][0] = dml_min(locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3592
locals->ReturnBWPerState[i][0] = dml_min(locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3615
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3774
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3783
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3793
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3809
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3819
locals->PSCL_FACTOR_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3827
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3835
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3924
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3946
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3974
locals->MaximumSwathWidth[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4117
if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4171
dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4422
locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4463
locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4467
locals->EffectiveLBLatencyHidingSourceLinesChroma = dml_min(locals->MaxLineBufferLines,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4472
locals->EffectiveDETLBLinesLuma = dml_floor(locals->LinesInDETLuma + dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4484
locals->EffectiveDETLBLinesChroma = dml_floor(locals->LinesInDETChroma + dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4489
locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5047
mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][0] = dml_min(mode_lib->vba.ReturnBusWidth *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
134
* dml_min((double) recout_width, (double) hactive / 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
603
log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
134
* dml_min((double) recout_width, (double) hactive / 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
603
log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1415
*dpte_row_height = dml_min(128,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1427
*dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1500
locals->PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1509
locals->PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1518
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1541
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1551
locals->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1560
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1697
locals->SwathWidthY[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2175
dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2224
locals->VStartup[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2234
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2741
dml_min(mode_lib->vba.DCCRate[k], DCCRateLimit);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2755
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2796
mode_lib->vba.SmallestVBlank = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2958
SwathWidth = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3232
min_row_time = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3236
min_row_time = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3252
min_row_time = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3468
dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[0][0][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3701
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3863
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3872
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3882
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3898
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3908
locals->PSCL_FACTOR_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3916
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3924
* dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4013
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4035
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4063
locals->MaximumSwathWidth[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4211
if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4265
dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4538
dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5051
locals->MaxTotalVerticalActiveAvailableBandwidth[i][0] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5360
mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5364
mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5429
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5443
WritebackDRAMClockChangeLatencyMargin = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5449
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
847
*DestinationLinesForPrefetch = dml_min(*DestinationLinesForPrefetch, 63.75);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
110
* dml_min((double) recout_width, (double) hactive / 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
603
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
728
vp_width = dml_min(full_src_vp_width, src_hactive_half);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
731
vp_height = dml_min(full_src_vp_width, src_hactive_half);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1370
max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1371
max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1741
*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1749
*dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1838
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1841
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1847
* dml_max(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1863
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1866
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1871
* dml_max3(v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2391
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2427
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2436
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[x]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2912
v->VStartupMargin = dml_min(v->VStartupMargin, margin);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3330
min_row_time = dml_min(dpte_row_height * LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3332
min_row_time = dml_min(meta_row_height * LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3343
min_row_time = dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3667
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3669
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3674
* dml_max3(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3680
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3683
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3685
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k] * dml_max5(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3687
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3721
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3722
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3969
dml_min(600.0, v->PHYCLKPerState[i]) * 10,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4603
v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4695
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5181
mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5183
mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5213
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5228
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5919
AverageReadBandwidth = AverageReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(DCCRateLuma[k], MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5929
AverageReadBandwidth = AverageReadBandwidth + ReadBandwidthPlaneChroma[k] / dml_min(DCCRateChroma[k], MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5938
PartOfBurstThatFitsInROB = dml_min(StutterPeriod * TotalDataReadBandwidth, ROBBufferSizeInKByte * 1024 * AverageDCCCompressionRate);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5968
SmallestVBlank = dml_min(SmallestVBlank, VBlankTime);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6222
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6224
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6250
swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (long) dml_ceil(SwathWidthY[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6254
swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, (long) dml_ceil(SwathWidthC[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6262
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (long) dml_ceil(SwathWidthY[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6266
swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, (long) dml_ceil(SwathWidthC[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6511
v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * (1 + mode_lib->vba.PercentMarginOverMinimumRequiredDCFCLK / 100)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
952
dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
60
* dml_min((double)recout_width, (double)hactive / ((unsigned int)odm_combine*2))
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
699
vp_width = dml_min(full_src_vp_width, src_hactive_odm);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
702
vp_height = dml_min(full_src_vp_width, src_hactive_odm);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1058
prefetch_bw_pr = dml_min(1, myPipe->VRatio) * prefetch_bw_pr;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1108
dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1570
max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1571
max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1940
*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1948
*dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2004
double IdealFabricAndSDPPortBandwidthPerState = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2009
v->ReturnBW = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2013
v->ReturnBW = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2042
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2046
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2051
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2064
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2068
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2072
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2458
VMDataOnlyReturnBW = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2459
dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2632
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2685
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3543
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3545
min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3559
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3721
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3950
v->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3954
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3960
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3968
v->PSCL_FACTOR_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3972
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3976
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3978
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4014
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4015
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4295
dml_min(600.0, v->PHYCLKPerState[i]) * 10,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5036
double IdealFabricAndSDPPortBandwidthPerState = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5040
double PixelDataOnlyReturnBWPerState = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5043
double PixelMixedWithVMDataReturnBWPerState = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5076
v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5077
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5130
VMDataOnlyReturnBWPerState = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5131
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5630
v->LBLatencyHidingSourceLinesY = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5634
v->LBLatencyHidingSourceLinesC = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5675
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5687
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6395
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6407
+ ReadBandwidthPlaneChroma[k] / dml_min(NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6437
EffectiveCompressedBufferSize = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6440
+ dml_min((ROBBufferSizeInKByte * 1024 - COMPBUF_RESERVED_SPACE_64B * 64) * AverageDCCCompressionRate,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6450
EffectiveCompressedBufferSize = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6507
PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*StutterPeriod * TotalDataReadBandwidth, EffectiveCompressedBufferSize);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6853
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6855
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6890
swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6894
swath_width_chroma_ub[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6903
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6907
swath_width_chroma_ub[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7181
v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
59
* dml_min((double) recout_width, (double) hactive / ((unsigned int) odm_combine * 2)) / pclk_freq_in_mhz / (double) req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
693
vp_width = dml_min(full_src_vp_width, src_hactive_odm);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
696
vp_height = dml_min(full_src_vp_width, src_hactive_odm);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1076
prefetch_bw_pr = dml_min(1, myPipe->VRatio) * prefetch_bw_pr;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1126
dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1587
max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1588
max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1957
*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1965
*dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2021
double IdealFabricAndSDPPortBandwidthPerState = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2027
v->ReturnBW = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2031
v->ReturnBW = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2060
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2064
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2069
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2082
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2086
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2090
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2477
VMDataOnlyReturnBW = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2478
dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2651
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2704
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3649
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3651
min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3665
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3827
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4041
v->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4045
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4051
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4059
v->PSCL_FACTOR_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4063
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4067
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4069
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4105
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4106
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4382
dml_min(600.0, v->PHYCLKPerState[i]) * 10,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5122
double IdealFabricAndSDPPortBandwidthPerState = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5126
double PixelDataOnlyReturnBWPerState = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5129
double PixelMixedWithVMDataReturnBWPerState = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5162
v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5163
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5216
VMDataOnlyReturnBWPerState = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5217
dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5724
v->LBLatencyHidingSourceLinesY = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5728
v->LBLatencyHidingSourceLinesC = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5769
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5781
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6490
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6502
+ ReadBandwidthPlaneChroma[k] / dml_min(NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6532
EffectiveCompressedBufferSize = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6535
+ dml_min((ROBBufferSizeInKByte * 1024 - COMPBUF_RESERVED_SPACE_64B * 64) * AverageDCCCompressionRate,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6545
EffectiveCompressedBufferSize = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6602
PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*StutterPeriod * TotalDataReadBandwidth, EffectiveCompressedBufferSize);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6944
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6946
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6980
swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6984
swath_width_chroma_ub[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6993
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6997
swath_width_chroma_ub[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7269
v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7335
vblank_size = (unsigned int) dml_min(vblank_actual, vblank_avail);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
147
* dml_min((double) recout_width, (double) hactive / ((unsigned int) odm_combine * 2)) / pclk_freq_in_mhz / (double) req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
781
vp_width = dml_min(full_src_vp_width, src_hactive_odm);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
784
vp_height = dml_min(full_src_vp_width, src_hactive_odm);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1950
v->MaximumSwathWidthLuma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1952
v->MaximumSwathWidthChroma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3300
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
792
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
842
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1107
NextDETBufferPieceInKByte = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1378
*OutBpp = dml32_TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1641
MaxLinkBPP = dml_min(MaxLinkBPP, 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1643
MaxLinkBPP = dml_min(MaxLinkBPP, 32);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1648
MaxLinkBPP = dml_min(MaxLinkBPP, 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1650
MaxLinkBPP = dml_min(MaxLinkBPP, 32);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1812
SurfaceSizeInMALL[k] = dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1815
ReadBlockWidthY[k])) * dml_min(dml_ceil(SurfaceHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1822
dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1826
dml_min(dml_ceil(SurfaceHeightC[k], ReadBlockHeightC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1834
(dml_min(dml_ceil(DCCMetaPitchY[k], 8 * Read256BytesBlockWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1838
* dml_min(dml_ceil(SurfaceHeightY[k], 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1845
dml_min(dml_ceil(DCCMetaPitchC[k], 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1852
dml_min(dml_ceil(SurfaceHeightC[k], 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1863
SurfaceSizeInMALL[k] = dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1865
dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1870
dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1872
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1878
(dml_ceil(dml_min(DCCMetaPitchY[k], ViewportWidthY[k] + 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1881
dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1887
dml_ceil(dml_min(DCCMetaPitchC[k], ViewportWidthC[k] + 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1890
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
221
*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatio /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
224
*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
227
DPPCLKUsingSingleDPPLuma = PixelClock * dml_max3(VTaps / 6 * dml_min(1, HRatio), HRatio * VRatio /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
239
*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
242
*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
244
DPPCLKUsingSingleDPPChroma = PixelClock * dml_max3(VTapsChroma / 6 * dml_min(1, HRatioChroma),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2456
*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2497
*dpte_row_height = dml_min(*PixelPTEReqWidth, MacroTileWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3146
DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3680
dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, __DML_VBA_MAX_DST_Y_PRE__);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4215
min_row_time = dml_min(dpte_row_height *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4218
min_row_time = dml_min(meta_row_height *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4232
dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4405
LBLatencyHidingSourceLinesY[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4406
LBLatencyHidingSourceLinesC[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4454
ActiveClockChangeLatencyHiding = dml_min(ActiveClockChangeLatencyHidingY,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4479
ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMargin[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4481
ActiveFCLKChangeLatencyMargin[k] = dml_min(ActiveFCLKChangeLatencyMargin[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5404
max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5405
max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5709
/ dml_min(NetDCCRateLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5737
/ dml_min(NetDCCRateChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5791
EffectiveCompressedBufferSize = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5796
+ dml_min(((double) ROBBufferSizeInKByte * 1024 - CompbufReservedSpace64B * 64)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5813
EffectiveCompressedBufferSize = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5915
PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*StutterPeriod * TotalDataReadBandwidth,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6336
DETSwathLatencyHidingUs = dml_min(DETSwathLatencyHidingYUs, DETSwathLatencyHidingCUs);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
753
SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
756
SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
794
swath_width_luma_ub[k] = dml_min(surface_width_ub_l,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
802
swath_width_luma_ub[k] = dml_min(surface_width_ub_l,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
810
swath_width_chroma_ub[k] = dml_min(surface_width_ub_c,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
817
swath_width_chroma_ub[k] = dml_min(surface_width_ub_c,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
830
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
835
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
841
swath_width_chroma_ub[k] = dml_min(surface_height_ub_c,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
848
swath_width_chroma_ub[k] = dml_min(surface_height_ub_c,
sys/dev/pci/drm/amd/display/dc/dml/dml_inline_defs.h
39
return dml_min(dml_min(a, b), c);
sys/dev/pci/drm/amd/display/dc/dml/dml_inline_defs.h
44
return dml_min(dml_min(a, b), dml_min(c, d));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1226
s->dst_y_prefetch_equ = dml_min(s->dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2039
min_row_time = dml_min(dpte_row_height * LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2041
min_row_time = dml_min(meta_row_height * LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2051
min_row_time = dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2198
max_vp_horz_width = (dml_uint_t)(dml_min((dml_float_t) MAS_vp_horz_limit, detile_buf_vp_horz_limit));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2199
max_vp_vert_height = (dml_uint_t)(dml_min((dml_float_t) MAS_vp_vert_limit, detile_buf_vp_vert_limit));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2618
*dpte_row_height = (dml_uint_t)(dml_min(128, 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2655
*dpte_row_height = (dml_uint_t)(dml_min(*PixelPTEReqWidth, MacroTileWidth));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2774
MaxLinkBPP = dml_min(MaxLinkBPP, 16);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2776
MaxLinkBPP = dml_min(MaxLinkBPP, 32);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2782
MaxLinkBPP = dml_min(MaxLinkBPP, 16);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2784
MaxLinkBPP = dml_min(MaxLinkBPP, 32);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2897
s->LBLatencyHidingSourceLinesY[k] = (dml_uint_t)(dml_min((dml_float_t)p->MaxLineBufferLines, dml_floor((dml_float_t)p->LineBufferSize / (dml_float_t)p->LBBitPerPixel[k] / ((dml_float_t)p->SwathWidthY[k] / dml_max(p->HRatio[k], 1.0)), 1)) - (p->VTaps[k] - 1));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2898
s->LBLatencyHidingSourceLinesC[k] = (dml_uint_t)(dml_min((dml_float_t)p->MaxLineBufferLines, dml_floor((dml_float_t)p->LineBufferSize / (dml_float_t)p->LBBitPerPixel[k] / ((dml_float_t)p->SwathWidthC[k] / dml_max(p->HRatioChroma[k], 1.0)), 1)) - (p->VTapsChroma[k] - 1));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2935
s->ActiveClockChangeLatencyHiding = dml_min(s->ActiveClockChangeLatencyHidingY, s->ActiveClockChangeLatencyHidingC);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2953
s->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(s->ActiveDRAMClockChangeLatencyMargin[k], s->WritebackFCLKChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2954
s->ActiveFCLKChangeLatencyMargin[k] = dml_min(s->ActiveFCLKChangeLatencyMargin[k], s->WritebackDRAMClockChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3821
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] / dml_min(p->NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3836
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceChroma[k] / dml_min(p->NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3873
EffectiveCompressedBufferSize = dml_min((dml_float_t)p->CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3875
dml_min(((dml_float_t)p->ROBBufferSizeInKByte * 1024 - p->CompbufReservedSpace64B * 64) * AverageDCCCompressionRate,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3885
EffectiveCompressedBufferSize = dml_min((dml_float_t)p->CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3958
PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*p->StutterPeriod * p->TotalDataReadBandwidth, EffectiveCompressedBufferSize);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4369
SwathWidthY[k] = (dml_uint_t)(dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k], true)));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4371
SwathWidthY[k] = (dml_uint_t)(dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k], true)));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4407
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_l, dml_floor(ViewportXStart[k] + SwathWidthY[k] + Read256BytesBlockWidthY[k] - 1, Read256BytesBlockWidthY[k]) - dml_floor(ViewportXStart[k], Read256BytesBlockWidthY[k])));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4409
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4414
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_c, dml_floor(ViewportXStartC[k] + SwathWidthC[k] + Read256BytesBlockWidthC[k] - 1, Read256BytesBlockWidthC[k]) - dml_floor(ViewportXStartC[k], Read256BytesBlockWidthC[k])));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4416
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4426
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] + SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1, Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k])));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4428
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4433
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_c, dml_floor(ViewportYStartC[k] + SwathWidthC[k] + Read256BytesBlockHeightC[k] - 1, Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], Read256BytesBlockHeightC[k])));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4435
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4706
p->DCFCLKState[j] = dml_min(p->DCFCLKPerState, 1.05 * dml_max(s->DCFCLKRequiredForAverageBandwidth, s->DCFCLKRequiredForPeakBandwidth));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4763
SurfaceSizeInMALL[k] = (dml_uint_t)(dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1, ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k], ReadBlockWidthY[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4764
dml_min(dml_ceil(SurfaceHeightY[k], ReadBlockHeightY[k]), dml_floor(ViewportYStartY[k] + ViewportHeightY[k] + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) - dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4769
dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]), dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) - dml_floor(ViewportXStartC[k], ReadBlockWidthC[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4770
dml_min(dml_ceil(SurfaceHeightC[k], ReadBlockHeightC[k]), dml_floor(ViewportYStartC[k] + ViewportHeightC[k] + ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) - dml_floor(ViewportYStartC[k], ReadBlockHeightC[k])) * BytesPerPixelC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4774
dml_min(dml_ceil(SurfaceWidthY[k], 8 * Read256BytesBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + 8 * Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k]) - dml_floor(ViewportXStartY[k], 8 * Read256BytesBlockWidthY[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4775
dml_min(dml_ceil(SurfaceHeightY[k], 8 * Read256BytesBlockHeightY[k]), dml_floor(ViewportYStartY[k] + ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1, 8 * Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStartY[k], 8 * Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4778
dml_min(dml_ceil(SurfaceWidthC[k], 8 * Read256BytesBlockWidthC[k]), dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + 8 * Read256BytesBlockWidthC[k] - 1, 8 * Read256BytesBlockWidthC[k]) - dml_floor(ViewportXStartC[k], 8 * Read256BytesBlockWidthC[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4779
dml_min(dml_ceil(SurfaceHeightC[k], 8 * Read256BytesBlockHeightC[k]), dml_floor(ViewportYStartC[k] + ViewportHeightC[k] + 8 * Read256BytesBlockHeightC[k] - 1, 8 * Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], 8 * Read256BytesBlockHeightC[k])) * BytesPerPixelC[k] / 256);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4783
SurfaceSizeInMALL[k] = (dml_uint_t)(dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) * dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * BytesPerPixelY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4786
dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4787
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) * BytesPerPixelC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4791
dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + 8 * Read256BytesBlockWidthY[k] - 1), 8 * Read256BytesBlockWidthY[k]) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4792
dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1), 8 * Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4796
dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + 8 * Read256BytesBlockWidthC[k] - 1), 8 * Read256BytesBlockWidthC[k]) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4797
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 * Read256BytesBlockHeightC[k] - 1), 8 * Read256BytesBlockHeightC[k]) * BytesPerPixelC[k] / 256);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4978
NextDETBufferPieceInKByte = (dml_uint_t)(dml_min(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5384
*OutBpp = TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, false, Output,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5660
*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatio / dml_ceil((dml_float_t) HTaps / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5662
*PSCL_THROUGHPUT = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5665
DPPCLKUsingSingleDPPLuma = PixelClock * dml_max3(VTaps / 6 * dml_min(1, HRatio), HRatio * VRatio / *PSCL_THROUGHPUT, 1);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5675
*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatioChroma / dml_ceil((dml_float_t) HTapsChroma / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5677
*PSCL_THROUGHPUT_CHROMA = dml_min(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5679
DPPCLKUsingSingleDPPChroma = PixelClock * dml_max3(VTapsChroma / 6 * dml_min(1, HRatioChroma),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6187
dml_uint_t vblank_nom_input = (dml_uint_t)dml_min(vblank_actual, vblank_nom_default_in_line);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6195
dml_uint_t vblank_nom_max_allowed_capped = dml_min(vblank_nom_vsync_capped, max_allowed_vblank_nom);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6199
vblank_size = (dml_uint_t) dml_min(vblank_actual, vblank_avail);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6214
max_vstartup_lines = (dml_uint_t) dml_min(max_vstartup_lines, DML_MAX_VSTARTUP_START);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6399
CalculatePrefetchSchedule_params->VStartup = (dml_uint_t)(dml_min(s->MaxVStartup, s->MaximumVStartup[j][k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6940
mode_lib->ms.MaximumSwathWidthLuma[k] = dml_min(s->MaximumSwathWidthSupportLuma, mode_lib->ms.MaximumSwathWidthInLineBufferLuma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6941
mode_lib->ms.MaximumSwathWidthChroma[k] = dml_min(s->MaximumSwathWidthSupportChroma, mode_lib->ms.MaximumSwathWidthInLineBufferChroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9004
CalculatePrefetchSchedule_params->VStartup = (dml_uint_t)(dml_min(s->VStartupLines, s->MaxVStartupLines[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9058
locals->VStartup[k] = (dml_uint_t)(dml_min(s->VStartupLines, s->MaxVStartupLines[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
138
return dml_min(dml_min(x, y), z);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
143
return dml_min(dml_min(dml_min(x, y), z), w);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h
40
__DML_DLL_EXPORT__ dml_float_t dml_min(dml_float_t x, dml_float_t y);