sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1109

Tr0_equ = dml_max4(

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4758

+ dml_max4(

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1085

Tr0_oto = dml_max4((MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto, Tr0_trips, // PREVIOUS_ERROR (missing this term)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1254

Tr0_equ = dml_max4(

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1103

Tr0_oto = dml_max4((MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto, Tr0_trips, // PREVIOUS_ERROR (missing this term)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1272

Tr0_equ = dml_max4(

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1368

v->MinTTUVBlank[k] = dml_max4(v->Watermark.DRAMClockChangeWatermark,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1714

return dml_max4(PixelWordRate / 4.0, AverageTribyteRate / 4.0, HActiveTribyteRate / 4.0, 25.0) * 1.002;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3658

Tr0_oto = dml_max4(

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

3871

Tr0_equ = dml_max4((MetaRowByte + PixelPTEBytesPerRow *

sys/dev/pci/drm/amd/display/dc/dml/dml_inline_defs.h

64

return dml_max(dml_max4(a, b, c, d), e);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1207

s->Tr0_oto = dml_max4(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

1399

s->Tr0_equ = dml_max4((p->MetaRowByte + p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor) / s->prefetch_bw_equ, s->Tr0_trips, (s->LineTime - s->Tvm_equ) / 2, s->LineTime / 4);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

4594

return dml_max4(PixelWordRate / 4.0, AverageTribyteRate / 4.0, HActiveTribyteRate / 4.0, 25.0) * 1.002;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9615

locals->MinTTUVBlank[k] = dml_max4(

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c

167

return dml_max(dml_max4(a, b, c, d), e);

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h

45

__DML_DLL_EXPORT__ dml_float_t dml_max4(dml_float_t a, dml_float_t b, dml_float_t c, dml_float_t d);