Symbol: dml_max3
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3684
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4803
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4902
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3791
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4922
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5021
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2007
mode_lib->vba.UrgentOutOfOrderReturnPerChannel = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2093
mode_lib->vba.UrgentLatency = dml_max3(mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.UrgentLatencyPixelMixedWithVMData, mode_lib->vba.UrgentLatencyVMDataOnly);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2285
dml_max3(locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2293
dml_max3(locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2368
mode_lib->vba.total_dcn_read_bw_with_flip + dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2377
dml_max3(locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3212
TimeForFetchingMetaPTEImmediateFlip = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3222
TimeForFetchingRowInVBlankImmediateFlip = dml_max3((MetaRowBytes + DPTEBytesPerRow) * HostVMInefficiencyFactor / ImmediateFlipBW, UrgentLatency * (HostVMDynamicLevels + 1), LineTime / 4);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3716
+ dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3880
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4522
mode_lib->vba.UrgentLatency = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4854
+ dml_max3(locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4957
mode_lib->vba.total_dcn_read_bw_with_flip = mode_lib->vba.total_dcn_read_bw_with_flip + dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4980
mode_lib->vba.UrgentOutOfOrderReturnPerChannel = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1103
Tvm_equ = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1871
* dml_max3(v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2269
ReorderBytes = v->NumberOfChannels * dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2500
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2513
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2598
v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip + dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2610
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3156
return dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3302
TimeForFetchingMetaPTEImmediateFlip = dml_max3(Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3310
TimeForFetchingRowInVBlankImmediateFlip = dml_max3((MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3674
* dml_max3(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4538
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4862
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6371
ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6423
DCFCLKRequiredForAverageBandwidth = dml_max3(v->ProjectedDCFCLKDeepSleep[i][j],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6506
DCFCLKRequiredForPeakBandwidth = dml_max3(DCFCLKRequiredForPeakBandwidth, 2 * ExtraLatencyCycles
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
960
Tvm_oto = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
967
Tr0_oto = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1080
Tvm_oto = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto, Tvm_trips, LineTime / 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1248
Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2071
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2453
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2740
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2752
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2858
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2870
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3373
return dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3511
TimeForFetchingMetaPTEImmediateFlip = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3521
TimeForFetchingRowInVBlankImmediateFlip = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3959
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5020
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5205
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5295
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7018
ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7066
DCFCLKRequiredForAverageBandwidth = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7175
DCFCLKRequiredForPeakBandwidth = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1098
Tvm_oto = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto, Tvm_trips, LineTime / 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1266
Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2089
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2472
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2759
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2771
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2877
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2889
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3479
return dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3617
TimeForFetchingMetaPTEImmediateFlip = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3627
TimeForFetchingRowInVBlankImmediateFlip = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4050
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5106
* dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5291
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5381
+ dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7106
ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7152
DCFCLKRequiredForAverageBandwidth = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7263
DCFCLKRequiredForPeakBandwidth = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1373
v->MinTTUVBlank[k] = dml_max3(v->Watermark.FCLKChangeWatermark,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2983
* dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
532
* dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
227
DPPCLKUsingSingleDPPLuma = PixelClock * dml_max3(VTaps / 6 * dml_min(1, HRatio), HRatio * VRatio /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
244
DPPCLKUsingSingleDPPChroma = PixelClock * dml_max3(VTapsChroma / 6 * dml_min(1, HRatioChroma),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2717
ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3137
DCFCLKRequiredForPeakBandwidth = dml_max3(DCFCLKRequiredForPeakBandwidth,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3265
TWait = dml_max3(DRAMClockChangeLatency + UrgentLatency, SREnterPlusExitTime, UrgentLatency);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3267
TWait = dml_max3(FCLKChangeLatency + UrgentLatency, SREnterPlusExitTime, UrgentLatency);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3650
Tvm_oto = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3863
Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4173
TimeForFetchingMetaPTEImmediateFlip = dml_max3(Tno_bw + PDEAndMetaPTEBytesPerFrame *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4182
TimeForFetchingRowInVBlankImmediateFlip = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4664
return dml32_RoundToDFSGranularity(dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB), 1, DISPCLKDPPCLKVCOSpeed);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6196
*MaxPrefetchBandwidth = *MaxPrefetchBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6266
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6270
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1199
s->Tvm_oto = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1393
s->Tvm_equ = dml_max3(*p->Tno_bw + p->PDEAndMetaPTEBytesFrame * p->HostVMInefficiencyFactor / s->prefetch_bw_equ, s->Tvm_trips, s->LineTime / 4);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1755
TWait = dml_max3(DRAMClockChangeLatency + UrgentLatency, SREnterPlusExitTime, UrgentLatency);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1757
TWait = dml_max3(FCLKChangeLatency + UrgentLatency, SREnterPlusExitTime, UrgentLatency);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1820
return RoundToDFSGranularity(dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB), 1, DISPCLKDPPCLKVCOSpeed);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2006
TimeForFetchingMetaPTEImmediateFlip = dml_max3(Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2013
TimeForFetchingRowInVBlankImmediateFlip = dml_max3((MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW, UrgentLatency * (HostVMDynamicLevelsTrips + 1), LineTime / 4.0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4568
ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4701
s->DCFCLKRequiredForPeakBandwidth = dml_max3(s->DCFCLKRequiredForPeakBandwidth,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5665
DPPCLKUsingSingleDPPLuma = PixelClock * dml_max3(VTaps / 6 * dml_min(1, HRatio), HRatio * VRatio / *PSCL_THROUGHPUT, 1);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5679
DPPCLKUsingSingleDPPChroma = PixelClock * dml_max3(VTapsChroma / 6 * dml_min(1, HRatioChroma),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5994
*PrefetchBandwidth = *PrefetchBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6003
+ dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6104
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6108
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6140
*TotalBandwidthNotIncludingMALLPrefetch = *TotalBandwidthNotIncludingMALLPrefetch + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6145
*TotalBandwidthNotIncludingMALLPrefetch = *TotalBandwidthNotIncludingMALLPrefetch + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7900
s->ReorderingBytes = (dml_uint_t)(mode_lib->ms.soc.num_chans * dml_max3(mode_lib->ms.soc.urgent_out_of_order_return_per_channel_pixel_only_bytes,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8765
s->ReorderBytes = (dml_uint_t)(mode_lib->ms.soc.num_chans * dml_max3(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9621
locals->MinTTUVBlank[k] = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h
44
__DML_DLL_EXPORT__ dml_float_t dml_max3(dml_float_t x, dml_float_t y, dml_float_t z);