sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1097
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1132
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1137
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1173
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1180
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1194
mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1205
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1215
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1223
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1233
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1242
mode_lib->vba.DISPCLKWithRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1245
mode_lib->vba.DISPCLKWithoutRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1280
mode_lib->vba.GlobalDPPCLK = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1437
mode_lib->vba.LastPixelOfLineExtraWatermark = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1463
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1663
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1678
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1681
mode_lib->vba.DCFCLKDeepSleep = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1997
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2025
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2035
mode_lib->vba.MaximumMaxVStartupLines = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2204
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2206
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2208
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2242
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2299
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2301
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2304
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2372
mode_lib->vba.MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2374
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2380
mode_lib->vba.MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2416
/ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2429
/ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2662
mode_lib->vba.RemainingFillLevel = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2927
return dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2929
dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2931
return dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2986
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3001
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3003
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3120
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3124
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3141
TimeForFetchingRowInVBlankImmediateFlip = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3144
dml_max(UrgentLatencyPixelDataOnly, LineTime / 4.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3155
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3599
dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3649
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3828
* dml_max(mode_lib->vba.HRatio[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3831
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3841
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3846
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3853
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3859
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3920
locals->RequiredDISPCLK[i][j] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3976
locals->RequiredDISPCLK[i][j] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3988
locals->RequiredDISPCLK[i][j] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4344
/ dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4349
/ dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4418
mode_lib->vba.ProjectedDCFCLKDeepSleep[0][0] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4424
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4436
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4449
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4461
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4473
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4486
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4639
locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4668
- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4806
dml_max(mode_lib->vba.ReadBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4846
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4906
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4981
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4988
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5004
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
551
*VReadyOffsetPix = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
563
Tdm = dml_max(0.0, UrgentExtraLatency - TCalc);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
594
dst_y_prefetch_equ = VStartup - dml_max(TCalc + TWait, XFCRemoteSurfaceFlipDelay) / LineTime
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
598
Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
607
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
609
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
619
Tr0_oto = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
621
dml_max(UrgentLatencyPixelDataOnly, dml_max(LineTime - Tvm_oto, LineTime / 4)));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
663
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
667
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
682
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
685
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
687
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
719
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
723
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
732
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
741
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
746
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
754
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
836
MaxPartialSwath = dml_max(1U, MaxPartialSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1157
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1192
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1197
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1233
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1240
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1254
mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1265
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1275
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1283
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1293
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1302
mode_lib->vba.DISPCLKWithRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1305
mode_lib->vba.DISPCLKWithoutRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1340
mode_lib->vba.GlobalDPPCLK = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1699
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1714
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1717
mode_lib->vba.DCFCLKDeepSleep = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2033
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2061
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2071
mode_lib->vba.MaximumMaxVStartupLines = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2238
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2240
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2242
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2276
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2333
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2335
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2338
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2406
mode_lib->vba.MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2408
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2414
mode_lib->vba.MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2450
/ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2463
/ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2641
dml_max(mode_lib->vba.StutterEnterPlusExitWatermark, mode_lib->vba.UrgentWatermark))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2735
mode_lib->vba.RemainingFillLevel = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3000
return dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3002
dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3004
return dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3059
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3074
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3076
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3193
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3197
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3214
TimeForFetchingRowInVBlankImmediateFlip = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3217
dml_max(UrgentLatencyPixelDataOnly, LineTime / 4.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3228
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3706
dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3756
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3935
* dml_max(mode_lib->vba.HRatio[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3938
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3948
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3953
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3960
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3966
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4034
locals->RequiredDISPCLK[i][j] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4090
locals->RequiredDISPCLK[i][j] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4102
locals->RequiredDISPCLK[i][j] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4465
/ dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4470
/ dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4540
mode_lib->vba.ProjectedDCFCLKDeepSleep[0][0] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4546
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4558
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4571
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4583
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4595
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4608
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4761
locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4790
- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4925
dml_max(mode_lib->vba.ReadBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4965
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5025
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
504
mode_lib->vba.LastPixelOfLineExtraWatermark = dml_max(mode_lib->vba.LastPixelOfLineExtraWatermark, DataFabricLineDeliveryTimeLuma - DisplayPipeLineDeliveryTimeLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
508
mode_lib->vba.LastPixelOfLineExtraWatermark = dml_max(mode_lib->vba.LastPixelOfLineExtraWatermark, DataFabricLineDeliveryTimeChroma - DisplayPipeLineDeliveryTimeChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5097
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5104
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5120
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
614
*VReadyOffsetPix = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
626
Tdm = dml_max(0.0, UrgentExtraLatency - TCalc);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
654
dst_y_prefetch_equ = VStartup - dml_max(TCalc + TWait, XFCRemoteSurfaceFlipDelay) / LineTime
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
658
Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
667
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
669
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
679
Tr0_oto = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
681
dml_max(UrgentLatencyPixelDataOnly, dml_max(LineTime - Tvm_oto, LineTime / 4)));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
723
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
727
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
742
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
745
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
747
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
779
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
783
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
792
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
801
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
806
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
814
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
896
MaxPartialSwath = dml_max(1U, MaxPartialSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1081
line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
1083
line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1082
line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
1084
line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1047
*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1235
MaxPartialSwath = dml_max(1U, MaxPartialSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1481
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1516
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1521
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1557
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1564
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1578
locals->DPPCLKUsingSingleDPP[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1589
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1599
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1607
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1617
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1626
mode_lib->vba.DISPCLKWithRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1629
mode_lib->vba.DISPCLKWithoutRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1660
mode_lib->vba.GlobalDPPCLK = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2059
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2085
locals->MaxVStartupLines[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2089
locals->MaximumMaxVStartupLines = dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2260
dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2320
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2565
locals->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2567
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2573
locals->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2668
mode_lib->vba.RemainingFillLevel = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2766
mode_lib->vba.StutterBurstTime = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3014
return dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3016
dml_max(SREnterPlusExitTime, UrgentLatency));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3018
return dml_max(SREnterPlusExitTime, UrgentLatency);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3073
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3088
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3090
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3228
*final_flip_bw = dml_max(PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime), (MetaRowBytes + DPTEBytesPerRow) * HostVMInefficiencyFactor / (*DestinationLinesToRequestRowInImmediateFlip * LineTime));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3795
dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3845
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4024
* dml_max(mode_lib->vba.HRatio[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4027
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4037
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4042
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4049
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4055
+ dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4128
locals->RequiredDISPCLK[i][j] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4184
locals->RequiredDISPCLK[i][j] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4196
locals->RequiredDISPCLK[i][j] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4760
locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4784
- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4785
mode_lib->vba.MaxMaxVStartup[0][0] = dml_max(mode_lib->vba.MaxMaxVStartup[0][0], locals->MaximumVStartup[0][0][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4825
dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4911
- dml_max(locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5098
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5105
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5121
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5361
dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5365
dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / 2 / dml_max(HRatio[k] / 2, 1.0)), 1))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5516
*StutterEnterPlusExitWatermark = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5564
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5575
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5583
*DCFCLKDeepSleep = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
760
*VReadyOffsetPix = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
772
Tdm = dml_max(0.0, UrgentExtraLatency - TCalc);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
801
dst_y_prefetch_equ = VStartup - dml_max(TCalc + TWait, XFCRemoteSurfaceFlipDelay) / LineTime
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
805
Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
821
Tvm_oto = dml_max(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
822
dml_max(UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
828
Tr0_oto = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
830
dml_max(UrgentLatency * (HostVMDynamicLevels + 1), dml_max(LineTime - Tvm_oto, LineTime / 4)));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
912
TimeForFetchingMetaPTE = dml_max(*Tno_bw + (double) PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / *PrefetchBandwidth,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
913
dml_max(UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1), LineTime / 4));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
925
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
928
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
930
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
958
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
962
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
971
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
980
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
985
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
993
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1128
line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
1130
line_wait = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1148
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1151
*VRatioPrefetchY = dml_max((double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1153
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1162
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1166
*VRatioPrefetchC = dml_max(*VRatioPrefetchC,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1168
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1226
v->prefetch_vmrow_bw[k] = dml_max(prefetch_vm_bw, prefetch_row_bw);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1582
MaxPartialSwath = dml_max(1U, MaxPartialSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1654
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1656
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1821
v->WritebackDISPCLK = dml_max(v->WritebackDISPCLK,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1847
* dml_max(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1848
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1881
v->DPPCLKUsingSingleDPP[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1891
v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1894
v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1897
v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1900
v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1903
v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1906
v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1911
v->DISPCLKWithRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1914
v->DISPCLKWithoutRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1946
v->GlobalDPPCLK = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2312
v->WritebackDelay[v->VoltageLevel][k] = dml_max(v->WritebackDelay[v->VoltageLevel][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2333
v->MaxVStartupLines[k] = v->VTotal[k] - v->VActive[k] - dml_max(1.0, dml_ceil((double) v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2338
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2425
v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2432
v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[x];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2550
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2719
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2844
v->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2846
dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2852
v->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3130
return dml_max(DRAMClockChangeLatency + UrgentLatency,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3131
dml_max(SREnterPlusExitTime, UrgentLatency));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3133
return dml_max(SREnterPlusExitTime, UrgentLatency);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3175
Line_length = dml_max((double) WritebackDestinationWidth, dml_ceil(WritebackDestinationWidth / 6.0, 1) * WritebackVTaps);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3197
VReadyOffsetPix = dml_max(150.0 / DPPCLK, TotalRepeaterDelayTime + 20 / DCFClkDeepSleep + 10 / DPPCLK) * PixelClock;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3319
*final_flip_bw = dml_max(PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3651
v->WritebackRequiredDISPCLK = dml_max(v->WritebackRequiredDISPCLK,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3713
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3714
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3718
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3719
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3847
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3901
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3912
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->WritebackRequiredDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4505
v->WritebackDelayTime[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4531
- dml_max(1.0, dml_ceil(1.0 * v->WritebackDelayTime[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4532
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4813
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4985
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4987
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4993
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4995
v->AlignedDCCMetaPitchC[k] = dml_ceil(dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]), 64.0 * v->Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5181
mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5183
mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5282
*StutterEnterPlusExitWatermark = dml_max(SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep, TimeToFinishSwathTransferStutterCriticalPlane);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5331
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(1.1 * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma, 1.1 * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5335
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(mode_lib->vba.DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5343
*DCFCLKDeepSleep = dml_max(8.0, ReadBandwidth / ReturnBusWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5346
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5941
StutterBurstTime = dml_max(StutterBurstTime, LinesToFinishSwathTransferStutterCriticalPlane * BytePerPixelYCriticalPlane * SwathWidthYCriticalPlane / ReturnBW);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6340
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6342
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6442
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6453
* dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4) * ExpectedPrefetchBWAcceleration;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6487
DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(DCFCLKRequiredForPeakBandwidthPerPlane[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6512
* dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
950
dst_y_prefetch_equ = VStartup - (Tsetup + dml_max(TWait + TCalc, v->Tdmdl[k])) / LineTime
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
954
Lsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1237
line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1239
line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1059
max_Tsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1061
prefetch_bw_oto = dml_max(prefetch_bw_pr, prefetch_sw_bytes / max_Tsw);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1063
min_Lsw = dml_max(1, dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1064
Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1107
dst_y_prefetch_equ = VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1112
dep_bytes = dml_max(PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor, MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1307
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1315
*VRatioPrefetchY = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1318
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1332
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1341
*VRatioPrefetchC = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1344
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1443
*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1760
MaxPartialSwath = dml_max(1U, MaxPartialSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1841
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1843
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2024
v->WritebackDISPCLK = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2050
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2052
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2080
v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2088
v->DISPCLKWithRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2092
v->DISPCLKWithoutRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2096
v->DISPCLKWithRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2100
v->DISPCLKWithoutRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2104
v->DISPCLKWithRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2107
v->DISPCLKWithoutRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2113
v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping, v->WritebackDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2114
v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping, v->WritebackDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2134
v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2518
v->WritebackDelay[v->VoltageLevel][k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2545
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2563
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2827
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2963
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3086
v->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3088
dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3092
v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3154
+ dml_max(1.0, dml_ceil(v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1.0))
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3196
MaxPerPlaneVActiveWRBandwidth = dml_max(MaxPerPlaneVActiveWRBandwidth, WRBandwidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3348
return dml_max(DRAMClockChangeLatency + UrgentLatency, dml_max(SREnterPlusExitTime, UrgentLatency));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3350
return dml_max(SREnterPlusExitTime, UrgentLatency);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3392
Line_length = dml_max((double) WritebackDestinationWidth, dml_ceil(WritebackDestinationWidth / 6.0, 1) * WritebackVTaps);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3426
*VReadyOffsetPix = dml_ceil(dml_max(150.0 / DPPCLK, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / DPPCLK) * PixelClock, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3532
v->final_flip_bw[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3933
v->WritebackRequiredDISPCLK = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4006
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4007
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4011
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4012
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4158
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4227
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4239
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->WritebackRequiredDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4976
v->WritebackDelayTime[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5005
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5014
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5265
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5398
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5400
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5407
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5410
dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5632
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5636
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5793
v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5798
v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5806
*DCFCLKDeepSleep = dml_max(8.0, __DML_MIN_DCFCLK_FACTOR__ * ReadBandwidth / ReturnBusWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5809
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6531
StutterBurstTime = dml_max(StutterBurstTime, LinesToFinishSwathTransferStutterCriticalPlane * BytePerPixelYCriticalPlane * SwathWidthYCriticalPlane / ReturnBW);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6552
*StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6553
*Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6989
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6991
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7098
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7115
* dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4) * ExpectedPrefetchBWAcceleration;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7152
DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7181
v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1077
max_Tsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1079
prefetch_bw_oto = dml_max(prefetch_bw_pr, prefetch_sw_bytes / max_Tsw);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1081
min_Lsw = dml_max(1, dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1082
Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1125
dst_y_prefetch_equ = VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1130
dep_bytes = dml_max(PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor, MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1325
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1333
*VRatioPrefetchY = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1336
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1350
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1359
*VRatioPrefetchC = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1362
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1460
*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1777
MaxPartialSwath = dml_max(1U, MaxPartialSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1858
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1860
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2042
v->WritebackDISPCLK = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2068
* dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2070
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2098
v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2106
v->DISPCLKWithRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2110
v->DISPCLKWithoutRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2114
v->DISPCLKWithRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2118
v->DISPCLKWithoutRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2122
v->DISPCLKWithRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2125
v->DISPCLKWithoutRamping = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2131
v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping, v->WritebackDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2132
v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping, v->WritebackDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2152
v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2537
v->WritebackDelay[v->VoltageLevel][k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2581
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2846
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2982
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3105
v->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3107
dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3111
v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3215
MaxPerPlaneVActiveWRBandwidth = dml_max(MaxPerPlaneVActiveWRBandwidth, WRBandwidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3454
return dml_max(DRAMClockChangeLatency + UrgentLatency, dml_max(SREnterPlusExitTime, UrgentLatency));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3456
return dml_max(SREnterPlusExitTime, UrgentLatency);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3498
Line_length = dml_max((double) WritebackDestinationWidth, dml_ceil(WritebackDestinationWidth / 6.0, 1) * WritebackVTaps);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3532
*VReadyOffsetPix = dml_ceil(dml_max(150.0 / DPPCLK, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / DPPCLK) * PixelClock, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3638
v->final_flip_bw[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4024
v->WritebackRequiredDISPCLK = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4097
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4098
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4102
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4103
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4248
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4314
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4326
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->WritebackRequiredDISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5064
v->WritebackDelayTime[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5100
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5351
- dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5484
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5486
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5493
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5496
dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5726
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5730
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5887
v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5892
v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5900
*DCFCLKDeepSleep = dml_max(8.0, __DML_MIN_DCFCLK_FACTOR__ * ReadBandwidth / ReturnBusWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5903
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6626
StutterBurstTime = dml_max(StutterBurstTime, LinesToFinishSwathTransferStutterCriticalPlane * BytePerPixelYCriticalPlane * SwathWidthYCriticalPlane / ReturnBW);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6647
*StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6648
*Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7079
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7081
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7184
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7202
* dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4) * ExpectedPrefetchBWAcceleration;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7239
DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7269
v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7339
MaxVStartup = vblank_size - dml_max(1.0, dml_ceil(WritebackDelayTime / line_time_us, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
105
v->DISPCLK_calculated = dml_max(v->DISPCLK_calculated,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1237
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1240
v->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1377
v->MinTTUVBlank[k] = dml_max(v->Watermark.StutterEnterPlusExitWatermark,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1445
+ dml_max(1.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1939
* dml_max(mode_lib->vba.HRatio[k], 1.0) / mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1940
/ (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1945
* dml_max(mode_lib->vba.HRatioChroma[k], 1.0) / mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1947
+ dml_max(dml_ceil(mode_lib->vba.VRatioChroma[k], 1.0) - 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2230
mode_lib->vba.WritebackRequiredDISPCLK = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2249
mode_lib->vba.RequiredDISPCLK[i][j] = dml_max(mode_lib->vba.RequiredDISPCLK[i][j],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2936
dml_max(mode_lib->vba.WritebackDelayTime[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2967
- dml_max(1.0, dml_ceil(1.0 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2976
mode_lib->vba.MaxMaxVStartup[i][j] = dml_max(mode_lib->vba.MaxMaxVStartup[i][j],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3632
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.SurfaceWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3636
dml_max(mode_lib->vba.DCCMetaPitchY[k], mode_lib->vba.SurfaceWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3647
dml_max(mode_lib->vba.PitchC[k], mode_lib->vba.SurfaceWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3651
dml_max(mode_lib->vba.DCCMetaPitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
618
dml_max(v->WritebackDelay[mode_lib->vba.VoltageLevel][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
699
mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) - dml_max(1.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
717
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
87
v->WritebackDISPCLK = dml_max(v->WritebackDISPCLK,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1566
*GlobalDPPCLK = dml_max(*GlobalDPPCLK, Dppclk[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1705
return dml_max(PixelClock / 4.0 * OutputBpp / 24.0, 25.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2321
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2323
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
248
*DPPCLKUsingSingleDPP = dml_max(DPPCLKUsingSingleDPPLuma, DPPCLKUsingSingleDPPChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2587
MaxPartialSwath = dml_max(1, (unsigned int) (vp_start_rot + *VInitPreFill - 1) % SwathHeight);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2591
MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill - 2) % SwathHeight);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2593
MaxPartialSwath = dml_max(1, (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2858
DCFClkDeepSleepPerSurface[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2866
DCFClkDeepSleepPerSurface[k] = dml_max(DCFClkDeepSleepPerSurface[k], PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2877
*DCFClkDeepSleep = dml_max(8.0, __DML_MIN_DCFCLK_FACTOR__ * ReadBandwidth / (double) ReturnBusWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2887
*DCFClkDeepSleep = dml_max(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2909
Line_length = dml_max((double) WritebackDestinationWidth,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3013
DCFCLKRequiredForAverageBandwidth = dml_max(ProjectedDCFClkDeepSleep[i][j], DPTEBandwidth / NormalEfficiency / ReturnBusWidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3039
PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3071
dml_max(1.0, ExpectedVRatioPrefetch) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3072
dml_max(1.0, ExpectedVRatioPrefetch / 4);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3115
dml_max(DCFCLKRequiredForPeakBandwidthPerSurface[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3147
dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3174
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3176
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3220
*VReadyOffsetPix = dml_ceil(dml_max(150.0 / Dppclk,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3269
TWait = dml_max(SREnterPlusExitTime, UrgentLatency);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3630
Tvm_trips_rounded = dml_max(Tvm_trips_rounded, LineTime / 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3631
Tr0_trips_rounded = dml_max(Tr0_trips_rounded, LineTime / 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3642
prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerSurface,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3643
prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3645
min_Lsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3646
min_Lsw = dml_max(min_Lsw, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3647
Lsw_oto = dml_ceil(4.0 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1.0) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3677
dst_y_prefetch_equ = VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3728
dep_bytes = dml_max(PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3948
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3957
dml_max((double) PrefetchSourceLinesY /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3962
*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3975
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3985
dml_max(*VRatioPrefetchC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3989
*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4099
*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4195
*final_flip_bw = dml_max(PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4405
LBLatencyHidingSourceLinesY[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4406
LBLatencyHidingSourceLinesC[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4626
SubViewportLinesNeededInMALL[k] = dml_max(sub_vp_lines_l, sub_vp_lines_c);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5946
StutterBurstTime = dml_max(StutterBurstTime,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5970
*StutterEfficiencyNotIncludingVBlank = dml_max(0.,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5972
*Z8StutterEfficiencyNotIncludingVBlank = dml_max(0.,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6229
CalculateBandwidthAvailableForImmediateFlip_val = CalculateBandwidthAvailableForImmediateFlip_val - dml_max(ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
957
DETBufferSizeInKByte[0] = dml_max(nomDETInKByte, dml_ceil(2.0 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
994
minDET_pipe = dml_max(128, dml_ceil(((double)RoundedUpMaxSwathSizeBytesY[k] +
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1130
double CalculateWriteBackDISPCLK = 1.01 * PixelClock * dml_max(
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1132
dml_max((WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * dml_ceil(WritebackDestinationWidth / 4.0, 1)
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1137
CalculateWriteBackDISPCLK = dml_max(CalculateWriteBackDISPCLK, 1.01 * PixelClock * dml_max(
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1139
dml_max((WritebackChromaVTaps * dml_ceil(1 / (2 * WritebackVRatio), 1) * dml_ceil(WritebackDestinationWidth / 2.0 / 2.0, 1)
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1166
min_ttu_vblank = dml_max(dlg_sys_param->t_sr_wm_us, min_ttu_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1168
min_ttu_vblank = dml_max(dlg_sys_param->t_mclk_wm_us, min_ttu_vblank);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1304
line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1306
line_wait = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1365
max_vinit_l = interlaced ? dml_max(vinit_l, vinit_bot_l) : vinit_l;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1366
max_vinit_c = interlaced ? dml_max(vinit_c, vinit_bot_c) : vinit_c;
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1410
t_vm_us = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1412
dml_max((double) vm_bytes / prefetch_bw, t_vm_us));
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1415
t_vm_us = dml_max(mode_lib->soc.urgent_latency_us, t_vm_us);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1417
t_vm_us = dml_max(vm_bytes / flip_bw, t_vm_us);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1421
t_r0_us = dml_max(dlg_sys_param->t_extra_us - t_vm_us, line_time_in_us - t_vm_us);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1424
t_r0_us = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1427
t_r0_us = dml_max((double) (line_time_in_us - t_vm_us), t_r0_us);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1430
t_r0_us = dml_max(mode_lib->soc.urgent_latency_us * 2.0, t_r0_us);
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1432
t_r0_us = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dml_inline_defs.h
54
return dml_max(dml_max(a, b), c);
sys/dev/pci/drm/amd/display/dc/dml/dml_inline_defs.h
59
return dml_max(dml_max(a, b), dml_max(c, d));
sys/dev/pci/drm/amd/display/dc/dml/dml_inline_defs.h
64
return dml_max(dml_max4(a, b, c, d), e);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1176
s->Tvm_trips_rounded = dml_max(s->Tvm_trips_rounded, s->LineTime / 4.0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1177
s->Tr0_trips_rounded = dml_max(s->Tr0_trips_rounded, s->LineTime / 4.0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1189
s->max_Tsw = (dml_max(p->PrefetchSourceLinesY, p->PrefetchSourceLinesC) * s->LineTime);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1192
s->prefetch_bw_oto = dml_max(s->prefetch_bw_pr, s->prefetch_sw_bytes / s->max_Tsw);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1194
s->min_Lsw_oto = dml_max(p->PrefetchSourceLinesY, p->PrefetchSourceLinesC) / __DML_MAX_VRATIO_PRE_OTO__;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1195
s->min_Lsw_oto = dml_max(s->min_Lsw_oto, 1.0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1196
s->Lsw_oto = dml_ceil(4.0 * dml_max(s->prefetch_sw_bytes / s->prefetch_bw_oto / s->LineTime, s->min_Lsw_oto), 1.0) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1225
s->dst_y_prefetch_equ = p->VStartup - (*p->TSetup + dml_max(p->TWait + p->TCalc, *p->Tdmdl)) / s->LineTime - (*p->DSTYAfterScaler + (dml_float_t) *p->DSTXAfterScaler / (dml_float_t)p->myPipe->HTotal);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1277
s->dep_bytes = dml_max(p->PDEAndMetaPTEBytesFrame * p->HostVMInefficiencyFactor, p->MetaRowByte + p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1446
*p->VRatioPrefetchY = dml_max(*p->VRatioPrefetchY, 1.0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1454
*p->VRatioPrefetchY = dml_max(*p->VRatioPrefetchY,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1469
*p->VRatioPrefetchC = dml_max(*p->VRatioPrefetchC, 1.0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1478
*p->VRatioPrefetchC = dml_max(*p->VRatioPrefetchC, (dml_float_t)p->MaxNumSwathC * p->SwathHeightC / (s->LinesToRequestPrefetchPixelData - (p->VInitPreFillC - 3.0) / 2.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1576
*p->prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1759
TWait = dml_max(SREnterPlusExitTime, UrgentLatency);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1839
Line_length = dml_max((dml_float_t) WritebackDestinationWidth, dml_ceil((dml_float_t)WritebackDestinationWidth / 6.0, 1.0) * WritebackVTaps);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1874
*VReadyOffsetPix = (dml_uint_t)(dml_ceil(dml_max(150.0 / Dppclk, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / Dppclk) * PixelClock, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2022
*final_flip_bw = dml_max(PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2427
MaxPartialSwath = (dml_uint_t)(dml_max(1, (dml_uint_t) (vp_start_rot + *VInitPreFill - 1) % SwathHeight));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2431
MaxPartialSwath = (dml_uint_t)(dml_max(1, (dml_uint_t) (*VInitPreFill - 2) % SwathHeight));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2433
MaxPartialSwath = (dml_uint_t)(dml_max(1, (dml_uint_t) (*VInitPreFill + SwathHeight - 2) % SwathHeight));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2897
s->LBLatencyHidingSourceLinesY[k] = (dml_uint_t)(dml_min((dml_float_t)p->MaxLineBufferLines, dml_floor((dml_float_t)p->LineBufferSize / (dml_float_t)p->LBBitPerPixel[k] / ((dml_float_t)p->SwathWidthY[k] / dml_max(p->HRatio[k], 1.0)), 1)) - (p->VTaps[k] - 1));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2898
s->LBLatencyHidingSourceLinesC[k] = (dml_uint_t)(dml_min((dml_float_t)p->MaxLineBufferLines, dml_floor((dml_float_t)p->LineBufferSize / (dml_float_t)p->LBBitPerPixel[k] / ((dml_float_t)p->SwathWidthC[k] / dml_max(p->HRatioChroma[k], 1.0)), 1)) - (p->VTapsChroma[k] - 1));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3092
p->SubViewportLinesNeededInMALL[k] = (dml_uint_t)(dml_max(s->sub_vp_lines_l, s->sub_vp_lines_c));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3156
DCFClkDeepSleepPerSurface[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3161
DCFClkDeepSleepPerSurface[k] = dml_max(DCFClkDeepSleepPerSurface[k], PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3173
*DCFClkDeepSleep = dml_max(8.0, __DML_MIN_DCFCLK_FACTOR__ * ReadBandwidth / (dml_float_t) ReturnBusWidth);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3183
*DCFClkDeepSleep = dml_max(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3980
StutterBurstTime = dml_max(StutterBurstTime, LinesToFinishSwathTransferStutterCriticalSurface * BytePerPixelYCriticalSurface * SwathWidthYCriticalSurface / p->ReturnBW);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3998
*p->StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (p->SRExitTime + StutterBurstTime) / *p->StutterPeriod) * 100;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3999
*p->Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (p->SRExitZ8Time + StutterBurstTime) / *p->StutterPeriod) * 100;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4289
*p->compbuf_reserved_space_64b = dml_max(*p->compbuf_reserved_space_64b,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4523
HostVMDynamicLevels = (dml_uint_t) dml_max(0, (dml_float_t) HostVMMaxNonCachedPageTableLevels - 1);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4525
HostVMDynamicLevels = (dml_uint_t) dml_max(0, (dml_float_t) HostVMMaxNonCachedPageTableLevels - 2);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4587
return dml_max(PixelClock / 4.0 * OutputBpp / 24.0, 25.0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4617
s->DCFCLKRequiredForAverageBandwidth = dml_max(p->ProjectedDCFCLKDeepSleep[j], s->DPTEBandwidth / s->NormalEfficiency / p->ReturnBusWidth);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4629
s->PrefetchPixelLinesTime[k] = dml_max(p->PrefetchLinesY[j][k], p->PrefetchLinesC[j][k]) * p->HTotal[k] / p->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4646
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = s->NoOfDPPState[k] * s->PixelDCFCLKCyclesRequiredInPrefetch[k] / s->PrefetchPixelLinesTime[k] * dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4684
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = dml_max(s->DCFCLKRequiredForPeakBandwidthPerSurface[k], s->ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4706
p->DCFCLKState[j] = dml_min(p->DCFCLKPerState, 1.05 * dml_max(s->DCFCLKRequiredForAverageBandwidth, s->DCFCLKRequiredForPeakBandwidth));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4859
DETBufferSizeInKByte[0] = (dml_uint_t) dml_max(128.0, dml_ceil(2.0 * ((dml_float_t) RoundedUpMaxSwathSizeBytesY[0] + (dml_float_t) RoundedUpMaxSwathSizeBytesC[0]) / 1024.0, ConfigReturnBufferSegmentSizeInkByte));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4890
minDET_pipe = (dml_uint_t)(dml_max(128, dml_ceil(((dml_float_t)RoundedUpMaxSwathSizeBytesY[k] + (dml_float_t)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, ConfigReturnBufferSegmentSizeInkByte)));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5683
*DPPCLKUsingSingleDPP = dml_max(DPPCLKUsingSingleDPPLuma, DPPCLKUsingSingleDPPChroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5704
*GlobalDPPCLK = dml_max(*GlobalDPPCLK, Dppclk[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6043
ret_val = ret_val - dml_max(ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6193
dml_uint_t vblank_nom_vsync_capped = dml_max(vblank_nom_input,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6204
max_vstartup_lines = vblank_size - (dml_uint_t) dml_max(1.0, dml_ceil(write_back_delay_us/line_time_us, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6928
mode_lib->ms.MaximumSwathWidthInLineBufferLuma = mode_lib->ms.ip.line_buffer_size_bits * dml_max(mode_lib->ms.cache_display_cfg.plane.HRatio[k], 1.0) / mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel[k] /
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6929
(mode_lib->ms.cache_display_cfg.plane.VTaps[k] + dml_max(dml_ceil(mode_lib->ms.cache_display_cfg.plane.VRatio[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6935
* dml_max(mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6938
+ dml_max(dml_ceil(mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7205
mode_lib->ms.WritebackRequiredDISPCLK = dml_max(mode_lib->ms.WritebackRequiredDISPCLK,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7222
mode_lib->ms.RequiredDISPCLK[j] = dml_max(mode_lib->ms.RequiredDISPCLK[j], mode_lib->ms.RequiredDISPCLKPerSurface[j][k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7862
mode_lib->ms.WritebackDelayTime[k] = dml_max(mode_lib->ms.WritebackDelayTime[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7892
s->MaxVStartupAllPlanes[j] = (dml_uint_t)(dml_max(s->MaxVStartupAllPlanes[j], s->MaximumVStartup[j][k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8075
dml_max(mode_lib->ms.cache_display_cfg.surface.PitchY[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8078
mode_lib->ms.support.AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k]), 64.0 * mode_lib->ms.Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8088
mode_lib->ms.support.AlignedCPitch[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.PitchC[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k]), mode_lib->ms.MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8090
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k]), 64.0 * mode_lib->ms.Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8343
dml_max(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8364
locals->Dispclk_calculated = dml_max(locals->Dispclk_calculated, CalculateRequiredDispclk(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8845
dml_max(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8920
s->MaxVStartupAllPlanes = (dml_uint_t)(dml_max(s->MaxVStartupAllPlanes, s->MaxVStartupLines[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9485
locals->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9487
locals->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9626
locals->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9707
+ dml_max(1.0, dml_ceil((dml_float_t) locals->WritebackDelay[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0))
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
159
return dml_max(dml_max(x, y), z);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
163
return dml_max(dml_max(a, b), dml_max(c, d));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
167
return dml_max(dml_max4(a, b, c, d), e);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h
43
__DML_DLL_EXPORT__ dml_float_t dml_max(dml_float_t x, dml_float_t y);
