sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5412

if (*OutBpp == 0 && PHYCLKD32PerState < 13500 / 32.0 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5426

if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5439

if (*OutBpp == 0 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5454

if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5471

if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5488

if (*OutBpp == 0 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7325

if (mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable_if_necessary && mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k] != 0)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7327

if ((mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable || mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable_if_necessary) && mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_n422 && !mode_lib->ms.ip.dsc422_native_support)