sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5409

if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr10) && PHYCLKD32PerState >= 10000 / 32.0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5422

if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr13p5) && *OutBpp == 0 && PHYCLKD32PerState >= 13500 / 32.0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5436

if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr20) && *OutBpp == 0 && PHYCLKD32PerState >= 20000 / 32) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5451

if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_hbr) && PHYCLKPerState >= 270) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5467

if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_hbr2) && *OutBpp == 0 && PHYCLKPerState >= 540) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5484

if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_hbr3) && *OutBpp == 0 && PHYCLKPerState >= 810) { // VBA_ERROR, vba code doesn't have hbr3 check

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7337

if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k && mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_na)

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

880

out->OutputLinkDPRate[location] = dml_dp_rate_na;