sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2764

if (Output == dml_dp2p0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5389

} else if (Output == dml_dp || Output == dml_dp2p0 || Output == dml_edp) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5393

if (Output == dml_dp || Output == dml_dp2p0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5401

if (Output == dml_dp2p0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5407

if (Output == dml_dp2p0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7260

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7296

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 && s->TotalSlots > 64)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7303

mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7320

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7333

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp2p0))

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7399

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 ||

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

794

out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

139

case dml_dp2p0: