sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

2766

} else if (DSCEnable && Output == dml_dp) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5389

} else if (Output == dml_dp || Output == dml_dp2p0 || Output == dml_edp) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5393

if (Output == dml_dp || Output == dml_dp2p0) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5457

if (Output == dml_dp) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5464

*OutputType = (Output == dml_dp) ? dml_output_type_dp : dml_output_type_edp;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5474

if (Output == dml_dp) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5481

*OutputType = (Output == dml_dp) ? dml_output_type_dp : dml_output_type_edp;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5491

if (Output == dml_dp) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5498

*OutputType = (Output == dml_dp) ? dml_output_type_dp : dml_output_type_edp;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5549

if ((Output == dml_hdmi || Output == dml_dp || Output == dml_edp) && ODMUse == dml_odm_use_policy_combine_4to1)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

5569

if (!(Output == dml_hdmi || Output == dml_dp || Output == dml_edp) && (ODMUse == dml_odm_use_policy_combine_4to1 || (ODMUse == dml_odm_use_policy_combine_as_needed &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7294

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp && s->TotalSlots > 63)

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7303

mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7320

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7331

mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp && mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_edp) ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7355

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp && (mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_split_1to2 ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7389

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1 && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp ||

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7398

if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp ||

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

792

out->OutputEncoder[location] = dml_dp;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

805

out->OutputEncoder[location] = dml_dp;

sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c

136

case dml_dp: