Symbol: dml_bool_t
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10090
dml_bool_t dml_mode_support(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10095
dml_bool_t is_mode_support;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10122
dml_bool_t dml_mode_programming(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10164
dml_bool_t mode_is_supported = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10201
dml_bool_t dml_get_is_phantom_pipe(struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
112
dml_bool_t DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
122
dml_bool_t *TotalAvailablePipesSupport,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1340
dml_bool_t Case1OK;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1341
dml_bool_t Case2OK;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1342
dml_bool_t Case3OK;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
170
dml_bool_t one_row_per_frame_fits_in_buffer[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
173
dml_bool_t UsesMALLForStaticScreen[]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1743
dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1744
dml_bool_t DRRDisplay,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
186
static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1860
dml_bool_t ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
189
static dml_float_t RoundToDFSGranularity(dml_float_t Clock, dml_bool_t round_up, dml_float_t VCOSpeed);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1907
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1911
dml_bool_t DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
192
dml_bool_t DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
193
dml_bool_t DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1953
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1955
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1967
dml_bool_t DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1972
dml_bool_t use_one_row_for_frame_flip,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
1978
dml_bool_t *ImmediateFlipSupportedForPipe)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2084
static dml_float_t RoundToDFSGranularity(dml_float_t Clock, dml_bool_t round_up, dml_float_t VCOSpeed)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2097
dml_bool_t DCCEnabled,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2098
dml_bool_t DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
219
dml_bool_t Interlace,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
220
dml_bool_t ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
223
dml_bool_t ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
234
dml_bool_t ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
235
dml_bool_t DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2378
dml_bool_t Interlace,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2379
dml_bool_t ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2382
dml_bool_t ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2450
dml_bool_t ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2451
dml_bool_t DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2463
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
247
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2693
static void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct dml_display_cfg_st *display_cfg, dml_bool_t ptoi_supported)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2713
dml_bool_t DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
279
dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
280
dml_bool_t DRRDisplay,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
292
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
296
dml_bool_t DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
315
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
317
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3209
dml_bool_t *NotEnoughUrgentLatencyHiding)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
329
dml_bool_t DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
334
dml_bool_t use_one_row_for_frame_flip,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
340
dml_bool_t *ImmediateFlipSupportedForPipe);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3422
dml_bool_t use_one_row_for_frame[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3424
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3432
dml_bool_t DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
363
dml_bool_t ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3643
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3649
dml_bool_t DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
372
static void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct dml_display_cfg_st *display_cfg, dml_bool_t ptoi_supported);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3775
dml_bool_t SinglePlaneCriticalSurface = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3776
dml_bool_t SinglePipeCriticalSurface = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3793
dml_bool_t FoundCriticalSurface = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3799
dml_bool_t SameTiming = true;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
381
dml_bool_t DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3924
dml_bool_t isInterlaceTiming = p->Interlace[k] && !p->ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4098
dml_bool_t NoChromaOrLinearSurfaces = true;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4297
dml_bool_t ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4301
dml_bool_t ViewportStationary[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
440
dml_bool_t *NotEnoughUrgentLatencyHiding);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
443
dml_bool_t DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4471
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4472
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4512
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4513
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4537
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4538
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4561
dml_bool_t DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4576
dml_bool_t DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4711
static dml_bool_t UnboundedRequest(enum dml_unbounded_requesting_policy UseUnboundedRequestingFinal,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4713
dml_bool_t NoChromaOrLinear,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4716
dml_bool_t ret_val = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4730
dml_bool_t DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4731
dml_bool_t ViewportStationary[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4757
dml_bool_t *ExceededMALLSize)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4813
dml_bool_t ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4815
dml_bool_t UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4834
dml_bool_t DETPieceAssignedToThisSurfaceAlready[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4835
dml_bool_t NextPotentialSurfaceToAssignDETPieceFound;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
495
dml_bool_t use_one_row_for_frame[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
497
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5024
dml_bool_t nomDETInKByteOverrideEnable, // VBA_DELTA, allow DV to override default DET size
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
505
dml_bool_t DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5346
dml_bool_t IsMainSurfaceUsingTheIndicatedTiming,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5364
dml_bool_t *RequiresDSC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5365
dml_bool_t *RequiresFEC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5371
dml_bool_t LinkDSCEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
550
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5515
dml_bool_t DSCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5525
dml_bool_t *TotalAvailablePipesSupport,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
556
dml_bool_t DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5720
dml_bool_t one_row_per_frame_fits_in_buffer[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5723
dml_bool_t UsesMALLForStaticScreen[])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5727
dml_bool_t CanAddAnotherSurfaceToMALL;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5769
dml_bool_t use_ideal_dram_bw_strobe,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5770
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5795
dml_bool_t use_ideal_dram_bw_strobe,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5796
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
581
dml_bool_t ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5840
dml_bool_t use_ideal_dram_bw_strobe,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5841
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
585
dml_bool_t ViewportStationary[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5871
dml_bool_t DSCEnabled,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5919
static noinline_for_stack dml_bool_t CalculateVActiveBandwithSupport(dml_uint_t NumberOfActiveSurfaces,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5921
dml_bool_t NotUrgentLatencyHiding[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5932
dml_bool_t NotEnoughUrgentLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5933
dml_bool_t CalculateVActiveBandwithSupport_val = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5961
dml_bool_t NotUrgentLatencyHiding[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5983
dml_bool_t *PrefetchBandwidthSupport)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5985
dml_bool_t NotEnoughUrgentLatencyHiding = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6096
dml_bool_t *ImmediateFlipBandwidthSupport)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6173
dml_bool_t ptoi_supported,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
627
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
628
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
642
dml_bool_t GPUVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
643
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
655
dml_bool_t DoUrgentLatencyAdjustment,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
660
static dml_bool_t UnboundedRequest(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
663
dml_bool_t NoChromaOrLinear,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
670
dml_bool_t DCCEnable[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
671
dml_bool_t ViewportStationary[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6715
dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
697
dml_bool_t *ExceededMALLSize);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
702
dml_bool_t ForceSingleDPP,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
704
dml_bool_t UnboundedRequestEnabled,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
726
dml_bool_t nomDETInKByteOverrideEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
735
dml_bool_t DSCEnabled,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
747
static dml_bool_t CalculateVActiveBandwithSupport(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
750
dml_bool_t NotUrgentLatencyHiding[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
765
dml_bool_t NotUrgentLatencyHiding[],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
787
dml_bool_t *PrefetchBandwidthSupport);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
79
dml_bool_t IsMainSurfaceUsingTheIndicatedTiming,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8304
dml_bool_t isInterlaceTiming;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
833
dml_bool_t *ImmediateFlipBandwidthSupport);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
97
dml_bool_t *RequiresDSC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
98
dml_bool_t *RequiresFEC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9836
dml_bool_t dummy_boolean[1];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9920
dml_bool_t is_plane1,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
997
static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st *scratch,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h
33
dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h
41
dml_bool_t is_plane1,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h
50
dml_bool_t use_ideal_dram_bw_strobe,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h
51
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h
58
dml_bool_t use_ideal_dram_bw_strobe,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h
59
dml_bool_t HostVMEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h
64
dml_bool_t dml_mode_support(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h
69
dml_bool_t dml_mode_programming(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.h
78
dml_bool_t dml_get_is_phantom_pipe(struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1105
dml_bool_t UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1110
dml_bool_t NoUrgentLatencyHiding[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1111
dml_bool_t NoUrgentLatencyHidingPre[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1113
dml_bool_t PrefetchAndImmediateFlipSupported;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1116
dml_bool_t NotEnoughTimeForDynamicMetadata[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1128
dml_bool_t use_one_row_for_frame[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1129
dml_bool_t use_one_row_for_frame_flip[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1140
dml_bool_t NoTimeToPrefetch[__DML_NUM_PLANES__]; /// <brief Prefetch schedule calculation result
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1144
dml_bool_t PrefetchModeSupported; /// <brief Is the prefetch mode (bandwidth and latency) supported
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1145
dml_bool_t ImmediateFlipSupported;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1146
dml_bool_t ImmediateFlipSupportedForPipe[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1166
dml_bool_t DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1192
dml_bool_t VREADY_AT_OR_AFTER_VSYNC[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1237
dml_bool_t PTE_BUFFER_MODE[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1241
dml_bool_t UsesMALLForStaticScreen[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1252
dml_bool_t USRRetrainingSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1274
dml_bool_t *DRRDisplay;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1275
dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1286
dml_bool_t GPUVMEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1288
dml_bool_t HostVMEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1292
dml_bool_t DynamicMetadataVMEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1293
dml_bool_t ImmediateFlipRequirement;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1294
dml_bool_t ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1301
dml_bool_t *Interlace;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1322
dml_bool_t *DynamicMetadataEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1330
dml_bool_t USRRetrainingRequiredFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1339
dml_bool_t SynchronizeTimingsFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1340
dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1341
dml_bool_t *DRRDisplay;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1372
dml_bool_t *WritebackEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1377
dml_bool_t UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1387
dml_bool_t *USRRetrainingSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1403
dml_bool_t GPUVMEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1404
dml_bool_t HostVMEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1409
dml_bool_t *PTEBufferModeOverrideEn;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1410
dml_bool_t *PTEBufferModeOverrideVal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1413
dml_bool_t *PTEBufferSizeNotExceeded;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1414
dml_bool_t *DCCMetaBufferSizeNotExceeded;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1452
dml_bool_t *use_one_row_for_frame;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1453
dml_bool_t *use_one_row_for_frame_flip;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1454
dml_bool_t *UsesMALLForStaticScreen;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1455
dml_bool_t *PTE_BUFFER_MODE;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1467
dml_bool_t ForceSingleDPP;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1479
dml_bool_t *ViewportStationary;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1515
dml_bool_t *UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1519
dml_bool_t *ViewportSizeSupportPerSurface;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1520
dml_bool_t *ViewportSizeSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1526
dml_bool_t UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1539
dml_bool_t SynchronizeTimingsFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1543
dml_bool_t ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1544
dml_bool_t *Interlace;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1569
dml_bool_t *DCCEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1570
dml_bool_t *WritebackEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1582
dml_bool_t *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1586
dml_bool_t EnhancedPrefetchScheduleAccelerationFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1601
dml_bool_t GPUVMEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1602
dml_bool_t HostVMEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1605
dml_bool_t DynamicMetadataEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1606
dml_bool_t DynamicMetadataVMEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1635
dml_bool_t *NotEnoughTimeForDynamicMetadata;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1647
dml_bool_t dummy_boolean[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1651
dml_bool_t dummy_boolean_array[2][__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1668
dml_bool_t MPCCombineMethodAsNeededForPStateChangeAndVoltage;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1669
dml_bool_t MPCCombineMethodAsPossible;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1670
dml_bool_t TotalAvailablePipesSupportNoDSC;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1674
dml_bool_t TotalAvailablePipesSupportDSC;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1678
dml_bool_t NoChromaOrLinear;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1689
dml_bool_t ImmediateFlipRequiredFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1690
dml_bool_t FullFrameMALLPStateMethod;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1691
dml_bool_t SubViewportMALLPStateMethod;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1692
dml_bool_t PhantomPipeMALLPStateMethod;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1693
dml_bool_t SubViewportMALLRefreshGreaterThan120Hz;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1699
dml_bool_t AllPrefetchModeTested;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1700
dml_bool_t AnyLinesForVMOrRowTooLarge;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1701
dml_bool_t is_max_pwr_state;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1702
dml_bool_t is_max_dram_pwr_state;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1703
dml_bool_t dram_clock_change_support;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1704
dml_bool_t f_clock_change_support;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1713
dml_bool_t dummy_boolean_array[2][__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1714
dml_bool_t dummy_boolean[1];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1724
dml_bool_t ImmediateFlipRequirementFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1728
dml_bool_t DestinationLineTimesForPrefetchLessThan2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1729
dml_bool_t VRatioPrefetchMoreThanMax;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1734
dml_bool_t AllPrefetchModeTested;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1756
dml_bool_t SynchronizedSurfaces[__DML_NUM_PLANES__][__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1777
dml_bool_t FoundCriticalSurface;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1808
dml_bool_t one_row_per_frame_fits_in_buffer[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
1835
dml_bool_t MyError;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
303
dml_bool_t use_ideal_dram_bw_strobe;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
359
dml_bool_t do_urgent_latency_adjustment;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
367
dml_bool_t UseNewDCN401SOCParameters;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
393
dml_bool_t gpuvm_enable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
394
dml_bool_t hostvm_enable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
420
dml_bool_t dsc422_native_support;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
421
dml_bool_t cursor_64bpp_support;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
431
dml_bool_t dynamic_metadata_vm_enabled;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
436
dml_bool_t dcc_supported;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
437
dml_bool_t ptoi_supported;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
453
dml_bool_t ScalerEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
470
dml_bool_t DCCEnable;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
476
dml_bool_t ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
485
dml_bool_t ViewportStationary;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
490
dml_bool_t FORCE_ONE_ROW_FOR_FRAME;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
528
dml_bool_t GPUVMEnable; /// <brief Set if any pipe has GPUVM enable
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
529
dml_bool_t HostVMEnable; /// <brief Set if any pipe has HostVM enable
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
535
dml_bool_t ForceOneRowForFrame[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
536
dml_bool_t PTEBufferModeOverrideEn[__DML_NUM_PLANES__]; //< brief when override enable; the DML will only check the given pte buffer and will use the pte buffer mode as is
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
537
dml_bool_t PTEBufferMode[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
546
dml_bool_t ViewportStationary[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
548
dml_bool_t ScalerEnabled[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
562
dml_bool_t DynamicMetadataEnable[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
571
dml_bool_t setup_for_tdlut[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
592
dml_bool_t DCCEnable[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
613
dml_bool_t Interlace[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
614
dml_bool_t DRRDisplay[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
625
dml_bool_t OutputMultistreamEn[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
634
dml_bool_t OutputDisabled[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
641
dml_bool_t WritebackEnable[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
659
dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is enabled; used in mode_programming
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
704
dml_bool_t UseMinimumRequiredDCFCLK; //<brief When set the mode_check stage will figure the min DCFCLK freq to support the given display configuration. User can tell use the output DCFCLK for mode programming.
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
705
dml_bool_t DRAMClockChangeRequirementFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
706
dml_bool_t FCLKChangeRequirementFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
707
dml_bool_t USRRetrainingRequiredFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
708
dml_bool_t EnhancedPrefetchScheduleAccelerationFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
710
dml_bool_t NomDETInKByteOverrideEnable; //<brief Nomimal DET buffer size for a pipe. If this size fit the required 2 swathes; DML will use this DET size
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
713
dml_bool_t DCCProgrammingAssumesScanDirectionUnknownFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
714
dml_bool_t SynchronizeTimingsFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
715
dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
716
dml_bool_t AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported; //<brief if set; the mode support will say mode is supported even though the DRAM clock change is not support (assuming the soc will be stay in max power state)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
717
dml_bool_t AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported; //<brief if set; the mode support will say mode is supported even though the Fabric clock change is not support (assuming the soc will be stay in max power state
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
725
dml_bool_t ModeIsSupported; //<brief Is the mode support any voltage and combine setting
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
726
dml_bool_t ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
728
dml_bool_t UnboundedRequestEnabled;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
732
dml_bool_t WritebackLatencySupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
733
dml_bool_t ScaleRatioAndTapsSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
734
dml_bool_t SourceFormatPixelAndScanSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
735
dml_bool_t MPCCombineMethodIncompatible;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
736
dml_bool_t P2IWith420;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
737
dml_bool_t DSCOnlyIfNecessaryWithBPP;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
738
dml_bool_t DSC422NativeNotSupported;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
739
dml_bool_t LinkRateDoesNotMatchDPVersion;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
740
dml_bool_t LinkRateForMultistreamNotIndicated;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
741
dml_bool_t BPPForMultistreamNotIndicated;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
742
dml_bool_t MultistreamWithHDMIOreDP;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
743
dml_bool_t MSOOrODMSplitWithNonDPLink;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
744
dml_bool_t NotEnoughLanesForMSO;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
745
dml_bool_t NumberOfOTGSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
746
dml_bool_t NumberOfHDMIFRLSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
747
dml_bool_t NumberOfDP2p0Support;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
748
dml_bool_t NonsupportedDSCInputBPC;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
749
dml_bool_t WritebackScaleRatioAndTapsSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
750
dml_bool_t CursorSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
751
dml_bool_t PitchSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
752
dml_bool_t ViewportExceedsSurface;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
753
dml_bool_t ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
754
dml_bool_t ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
755
dml_bool_t InvalidCombinationOfMALLUseForPStateAndStaticScreen;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
756
dml_bool_t InvalidCombinationOfMALLUseForPState;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
757
dml_bool_t ExceededMALLSize;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
758
dml_bool_t EnoughWritebackUnits;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
760
dml_bool_t ExceededMultistreamSlots;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
761
dml_bool_t ODMCombineTwoToOneSupportCheckOK;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
762
dml_bool_t ODMCombineFourToOneSupportCheckOK;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
763
dml_bool_t NotEnoughDSCUnits;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
764
dml_bool_t NotEnoughDSCSlices;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
765
dml_bool_t PixelsPerLinePerDSCUnitSupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
766
dml_bool_t DSCCLKRequiredMoreThanSupported;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
767
dml_bool_t DTBCLKRequiredMoreThanSupported;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
768
dml_bool_t LinkCapacitySupport;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
770
dml_bool_t ROBSupport[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
771
dml_bool_t PTEBufferSizeNotExceeded[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
772
dml_bool_t DCCMetaBufferSizeNotExceeded[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
773
dml_bool_t TotalVerticalActiveBandwidthSupport[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
778
dml_bool_t USRRetrainingSupport[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
779
dml_bool_t VActiveBandwithSupport[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
780
dml_bool_t PrefetchSupported[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
781
dml_bool_t DynamicMetadataSupported[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
782
dml_bool_t VRatioInPrefetchSupported[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
783
dml_bool_t DISPCLK_DPPCLK_Support[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
784
dml_bool_t TotalAvailablePipesSupport[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
785
dml_bool_t ModeSupport[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
786
dml_bool_t ViewportSizeSupport[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
787
dml_bool_t ImmediateFlipSupportedForState[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
789
dml_bool_t NoTimeForPrefetch[2][__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
790
dml_bool_t NoTimeForDynamicMetadata[2][__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
792
dml_bool_t MPCCombineEnable[__DML_NUM_PLANES__]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
795
dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is actually required; used in mode_programming
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
796
dml_bool_t FECEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the FEC is actually required
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
863
dml_bool_t DCCEnabledInAnySurface;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
879
dml_bool_t UnboundedRequestEnabledAllStates[2];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
881
dml_bool_t UnboundedRequestEnabledThisState;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
908
dml_bool_t use_one_row_for_frame[2][__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
909
dml_bool_t use_one_row_for_frame_flip[2][__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
910
dml_bool_t use_one_row_for_frame_this_state[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
911
dml_bool_t use_one_row_for_frame_flip_this_state[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
956
dml_bool_t RequiresDSC[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
957
dml_bool_t RequiresFEC[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
987
dml_bool_t MPCCombine[2][__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
988
dml_bool_t MPCCombineThisState[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
991
dml_bool_t SingleDPPViewportSizeSupportPerSurface[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
992
dml_bool_t ImmediateFlipSupportedForPipe[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
993
dml_bool_t NotUrgentLatencyHiding[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
994
dml_bool_t NotUrgentLatencyHidingPre[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
995
dml_bool_t PTEBufferSizeNotExceededPerState[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h
996
dml_bool_t DCCMetaBufferSizeNotExceededPerState[__DML_NUM_PLANES__];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
179
dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
201
dml_uint_t dml_round_to_multiple(dml_uint_t num, dml_uint_t multiple, dml_bool_t up)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
411
void dml_print_dml_mode_support_info(const struct dml_mode_support_info_st *support, dml_bool_t fail_only)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
44
dml_bool_t dml_util_is_420(enum dml_source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
46
dml_bool_t val = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
702
dml_bool_t dml_is_vertical_rotation(enum dml_rotation_angle Scan)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
704
dml_bool_t is_vert = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
766
dml_bool_t pipe_found = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h
37
__DML_DLL_EXPORT__ dml_bool_t dml_util_is_420(enum dml_source_format_class source_format);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h
49
__DML_DLL_EXPORT__ dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h
51
__DML_DLL_EXPORT__ dml_uint_t dml_round_to_multiple(dml_uint_t num, dml_uint_t multiple, dml_bool_t up);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h
52
__DML_DLL_EXPORT__ dml_bool_t dml_is_vertical_rotation(enum dml_rotation_angle scan);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.h
60
__DML_DLL_EXPORT__ void dml_print_dml_mode_support_info(const struct dml_mode_support_info_st *support, dml_bool_t fail_only);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
207
dml_bool_t dual_plane = is_dual_plane(source_format);
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
215
dml_bool_t interlaced = timing->Interlace[plane_idx];
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
29
static dml_bool_t is_dual_plane(enum dml_source_format_class source_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
31
dml_bool_t ret_val = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
46
dml_bool_t dual_plane = is_dual_plane((enum dml_source_format_class)(source_format));
sys/dev/pci/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c
67
dml_bool_t is_phantom_pipe;