dml32_RoundToDFSGranularity

2146

} else if (dml32_RoundToDFSGranularity(

1306

DISPCLKWithRampingRoundedToDFSGranularity = dml32_RoundToDFSGranularity(

1310

DISPCLKWithoutRampingRoundedToDFSGranularity = dml32_RoundToDFSGranularity(

1313

MaxDispclkRoundedDownToDFSGranularity = dml32_RoundToDFSGranularity(MaxDispclk, 0, DISPCLKDPPCLKVCOSpeed);

1568

*GlobalDPPCLK = dml32_RoundToDFSGranularity(*GlobalDPPCLK, 1, DISPCLKDPPCLKVCOSpeed);

4664

return dml32_RoundToDFSGranularity(dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB), 1, DISPCLKDPPCLKVCOSpeed);

247

double dml32_RoundToDFSGranularity(double Clock, bool round_up, double VCOSpeed);