Symbol: dml2_swizzle_mode
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
285
static enum dml2_swizzle_mode gfx_addr3_to_dml2_swizzle_mode(enum swizzle_mode_addr3_values addr3_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
287
enum dml2_swizzle_mode dml2_mode = dml2_sw_linear;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
314
static enum dml2_swizzle_mode gfx9_to_dml2_swizzle_mode(enum swizzle_mode_values gfx9_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
316
enum dml2_swizzle_mode dml2_mode = dml2_sw_64kb_2d;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
166
enum dml2_swizzle_mode tiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12032
enum dml2_swizzle_mode SurfaceTiling,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12220
enum dml2_swizzle_mode sw_mode = display_cfg->plane_descriptors[plane_idx].surface.tiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2003
enum dml2_swizzle_mode TilingFormat,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
505
static unsigned int dml_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
548
static int unsigned dml_get_gfx_version(enum dml2_swizzle_mode sw_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
576
enum dml2_swizzle_mode SurfaceTiling,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.h
34
void dml2_core_calcs_get_dpte_row_height(unsigned int *dpte_row_height, struct dml2_core_internal_display_mode_lib *mode_lib, bool is_plane1, enum dml2_source_format_class SourcePixelFormat, enum dml2_swizzle_mode SurfaceTiling, enum dml2_rotation_angle ScanDirection, unsigned int pitch, unsigned int GPUVMMinPageSizeKBytes);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
126
enum dml2_swizzle_mode SurfaceTiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
427
unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
460
bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
465
bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
482
int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
23
unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
24
bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
26
bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
27
int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode);