Symbol: dml2_options
sys/dev/pci/drm/amd/display/dc/core/dc.c
1092
dc->dml2_options.bb_from_dmub = init_params->bb_from_dmub;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1094
dc->dml2_options.bb_from_dmub = NULL;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5543
void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5545
dml2_options->callbacks.dc = dc;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5546
dml2_options->callbacks.build_scaling_params = &resource_build_scaling_params;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5547
dml2_options->callbacks.build_test_pattern_params = &resource_build_test_pattern_params;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5548
dml2_options->callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5549
dml2_options->callbacks.update_pipes_for_stream_with_slice_count = &resource_update_pipes_for_stream_with_slice_count;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5550
dml2_options->callbacks.update_pipes_for_plane_with_slice_count = &resource_update_pipes_for_plane_with_slice_count;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5551
dml2_options->callbacks.get_mpc_slice_index = &resource_get_mpc_slice_index;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5552
dml2_options->callbacks.get_mpc_slice_count = &resource_get_mpc_slice_count;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5553
dml2_options->callbacks.get_odm_slice_index = &resource_get_odm_slice_index;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5554
dml2_options->callbacks.get_odm_slice_count = &resource_get_odm_slice_count;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5555
dml2_options->callbacks.get_opp_head = &resource_get_opp_head;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5556
dml2_options->callbacks.get_otg_master_for_stream = &resource_get_otg_master_for_stream;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5557
dml2_options->callbacks.get_opp_heads_for_otg_master = &resource_get_opp_heads_for_otg_master;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5558
dml2_options->callbacks.get_dpp_pipes_for_plane = &resource_get_dpp_pipes_for_plane;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5559
dml2_options->callbacks.get_stream_status = &dc_state_get_stream_status;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5560
dml2_options->callbacks.get_stream_from_id = &dc_state_get_stream_from_id;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5561
dml2_options->callbacks.get_max_flickerless_instant_vtotal_increase = &dc_stream_get_max_flickerless_instant_vtotal_increase;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5562
dml2_options->callbacks.allocate_mcache = &resource_allocate_mcache;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5564
dml2_options->svp_pstate.callbacks.dc = dc;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5565
dml2_options->svp_pstate.callbacks.add_phantom_plane = &dc_state_add_phantom_plane;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5566
dml2_options->svp_pstate.callbacks.add_phantom_stream = &dc_state_add_phantom_stream;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5567
dml2_options->svp_pstate.callbacks.build_scaling_params = &resource_build_scaling_params;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5568
dml2_options->svp_pstate.callbacks.create_phantom_plane = &dc_state_create_phantom_plane;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5569
dml2_options->svp_pstate.callbacks.remove_phantom_plane = &dc_state_remove_phantom_plane;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5570
dml2_options->svp_pstate.callbacks.remove_phantom_stream = &dc_state_remove_phantom_stream;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5571
dml2_options->svp_pstate.callbacks.create_phantom_stream = &dc_state_create_phantom_stream;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5572
dml2_options->svp_pstate.callbacks.release_phantom_plane = &dc_state_release_phantom_plane;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5573
dml2_options->svp_pstate.callbacks.release_phantom_stream = &dc_state_release_phantom_stream;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5574
dml2_options->svp_pstate.callbacks.get_pipe_subvp_type = &dc_state_get_pipe_subvp_type;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5575
dml2_options->svp_pstate.callbacks.get_stream_subvp_type = &dc_state_get_stream_subvp_type;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5576
dml2_options->svp_pstate.callbacks.get_paired_subvp_stream = &dc_state_get_paired_subvp_stream;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5577
dml2_options->svp_pstate.callbacks.remove_phantom_streams_and_planes = &dc_state_remove_phantom_streams_and_planes;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5578
dml2_options->svp_pstate.callbacks.release_phantom_streams_and_planes = &dc_state_release_phantom_streams_and_planes;
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
209
if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) {
sys/dev/pci/drm/amd/display/dc/core/dc_vm_helper.c
50
dc->dml2_options.gpuvm_enable = true;
sys/dev/pci/drm/amd/display/dc/dc.h
1776
struct dml2_configuration_options dml2_options;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3061
dc->dml2_options.bbox_overrides.sr_exit_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3068
dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3076
dc->dml2_options.bbox_overrides.urgent_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3083
dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3091
dc->dml2_options.bbox_overrides.fclk_change_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3109
dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3114
dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3119
dc->dml2_options.bbox_overrides.sr_exit_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3127
dc->dml2_options.bbox_overrides.dram_num_chan =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3134
dc->dml2_options.bbox_overrides.dram_chanel_width_bytes =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3145
dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3146
dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3147
dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3148
dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3318
dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3320
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3323
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3326
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3329
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3332
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3335
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3338
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3343
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3349
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3355
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3361
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3367
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3373
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
3375
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
619
dc->dml2_options.bbox_overrides.sr_exit_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
626
dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
634
dc->dml2_options.bbox_overrides.urgent_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
641
dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
649
dc->dml2_options.bbox_overrides.fclk_change_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
667
dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
672
dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
677
dc->dml2_options.bbox_overrides.sr_exit_latency_us =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
685
dc->dml2_options.bbox_overrides.dram_num_chan =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
692
dc->dml2_options.bbox_overrides.dram_chanel_width_bytes =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
703
dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
704
dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
705
dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
706
dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
867
dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
869
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
872
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
875
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
878
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
881
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
884
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
887
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
893
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
899
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
905
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
911
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
917
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
923
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
925
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
356
dc->dml2_options.bbox_overrides.clks_table.num_states =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
358
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
360
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
362
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
364
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
366
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
368
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
371
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
372
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
374
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
376
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
378
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
380
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
382
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
384
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
386
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
392
dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latency_us;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
394
dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_5_soc.sr_exit_time_us;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
395
dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_5_soc.sr_enter_plus_exit_time_us;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
397
dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_5_soc.sr_exit_z8_time_us;
sys/dev/pci/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
398
dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_5_soc.sr_enter_plus_exit_z8_time_us;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
390
dc->dml2_options.bbox_overrides.clks_table.num_states =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
392
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
394
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
396
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
398
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
400
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
402
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
404
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
405
dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
407
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
409
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
411
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
413
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
415
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
417
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
419
dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
425
dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_51_soc.dram_clock_change_latency_us;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
427
dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_51_soc.sr_exit_time_us;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
428
dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_51_soc.sr_enter_plus_exit_time_us;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
430
dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_51_soc.sr_exit_z8_time_us;
sys/dev/pci/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
431
dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_51_soc.sr_enter_plus_exit_z8_time_us;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
82
struct dml2_options options;
sys/dev/pci/drm/amd/display/dc/inc/resource.h
649
void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2073
dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2522
dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2523
dc->dml2_options.use_native_soc_bb_construction = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2524
dc->dml2_options.minimize_dispclk_using_odm = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2526
resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2527
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2528
dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2529
dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2531
dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2532
dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2533
dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2534
dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2536
dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2537
dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2539
dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2540
dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2541
dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2542
dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2543
dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2544
dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2545
dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2547
dc->dml2_options.max_segments_per_hubp = 18;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2548
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2549
dc->dml2_options.map_dc_pipes_with_callbacks = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
2555
memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
1588
dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2017
dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2018
dc->dml2_options.use_native_soc_bb_construction = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2019
dc->dml2_options.minimize_dispclk_using_odm = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2021
resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2022
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2023
dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2024
dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2026
dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2027
dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2028
dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2029
dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2031
dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2032
dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2034
dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2035
dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2036
dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2037
dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2038
dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2039
dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2040
dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2042
dc->dml2_options.max_segments_per_hubp = 18;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2043
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
2046
memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2177
dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2178
dc->dml2_options.use_native_soc_bb_construction = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2179
dc->dml2_options.minimize_dispclk_using_odm = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2181
dc->dml2_options.minimize_dispclk_using_odm = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2182
dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2184
resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2185
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2187
dc->dml2_options.max_segments_per_hubp = 24;
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2188
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
2189
dc->dml2_options.override_det_buffer_size_kbytes = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2150
dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2151
dc->dml2_options.use_native_soc_bb_construction = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2152
dc->dml2_options.minimize_dispclk_using_odm = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2154
dc->dml2_options.minimize_dispclk_using_odm = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2155
dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2157
resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2158
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2160
dc->dml2_options.max_segments_per_hubp = 24;
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2161
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
2162
dc->dml2_options.override_det_buffer_size_kbytes = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2150
dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2151
dc->dml2_options.use_native_soc_bb_construction = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2152
dc->dml2_options.minimize_dispclk_using_odm = false;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2154
dc->dml2_options.minimize_dispclk_using_odm = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2155
dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2157
resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2158
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2160
dc->dml2_options.max_segments_per_hubp = 24;
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2161
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
2162
dc->dml2_options.override_det_buffer_size_kbytes = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
1622
dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2216
dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2217
dc->dml2_options.use_native_soc_bb_construction = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2218
dc->dml2_options.minimize_dispclk_using_odm = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2219
dc->dml2_options.map_dc_pipes_with_callbacks = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2220
dc->dml2_options.force_tdlut_enable = true;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2222
resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2223
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2224
dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2225
dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2227
dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2228
dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2229
dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2230
dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2232
dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2233
dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2235
dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2236
dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2237
dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2238
dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2239
dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2240
dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2241
dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2243
dc->dml2_options.max_segments_per_hubp = 20;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2244
dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;
sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
2250
memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));