Symbol: dml2_odm_mode
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
412
enum dml2_odm_mode odm_mode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
348
enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1240
enum dml2_odm_mode ODMMode,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1279
enum dml2_odm_mode ODMModeNoDSC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1280
enum dml2_odm_mode ODMModeDSC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1291
enum dml2_odm_mode ODMMode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3948
static enum dml2_odm_mode DecideODMMode(unsigned int HActive,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3959
enum dml2_odm_mode MinimumRequiredODMModeForMaxDispClock;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3960
enum dml2_odm_mode MinimumRequiredODMModeForMaxDSCHActive;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3961
enum dml2_odm_mode MinimumRequiredODMModeForMax420HActive;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3962
enum dml2_odm_mode ODMMode = dml2_odm_mode_bypass;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4002
enum dml2_odm_mode ODMUse,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4043
static bool ValidateODMMode(enum dml2_odm_mode ODMMode,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4108
enum dml2_odm_mode ODMUse,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4119
enum dml2_odm_mode *ODMMode,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4133
enum dml2_odm_mode DecidedODMMode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4217
enum dml2_odm_mode ODMModeNoDSC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4218
enum dml2_odm_mode ODMModeDSC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4487
enum dml2_odm_mode ODMMode,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
819
enum dml2_odm_mode ODMMode[],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
842
enum dml2_odm_mode MainSurfaceODMMode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1051
enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1072
enum dml2_odm_mode ODMModeNoDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1076
enum dml2_odm_mode ODMModeDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
124
enum dml2_odm_mode ODMMode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1579
enum dml2_odm_mode odm_mode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
1776
enum dml2_odm_mode *ODMMode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
280
enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
532
enum dml2_odm_mode ODMModeNoDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
533
enum dml2_odm_mode ODMModeDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
566
enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
655
enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
771
bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
41
bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
145
static bool increase_odm_combine_factor(enum dml2_odm_mode *odm_mode, int odms_calculated)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
182
static bool increase_odm_combine_factor(enum dml2_odm_mode *odm_mode, int odms_calculated)