sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

398

sizeof(struct dml2_hubp_pipe_mcache_regs));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

412

sizeof(struct dml2_hubp_pipe_mcache_regs));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

723

struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

726

struct dml2_hubp_pipe_mcache_regs mcache_regs_set[DML2_MAX_DCN_PIPES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

1025

memset(params->per_plane_pipe_mcache_regs, 0, DML2_MAX_PLANES * DML2_MAX_DCN_PIPES * sizeof(struct dml2_hubp_pipe_mcache_regs *));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

630

static void reset_mcache_allocations(struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

692

struct dml2_hubp_pipe_mcache_regs *mcache_regs)

sys/dev/pci/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

305

struct dml2_hubp_pipe_mcache_regs *mcache_regs);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

491

struct dml2_hubp_pipe_mcache_regs mcache_regs;

sys/dev/pci/drm/amd/display/dc/inc/hw/hubp.h

289

void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);