sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

27

case (dml2_core_internal_bw_max):

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2746

double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2748

double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2766

for (n = 0; n < dml2_core_internal_bw_max; n++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2804

double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

2824

for (n = 0; n < dml2_core_internal_bw_max; n++) { // sdp, dram

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6114

for (n = 0; n < dml2_core_internal_bw_max; n++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6318

double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6319

double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6320

double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6321

double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max])

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6378

for (unsigned int n = 0; n < dml2_core_internal_bw_max; n++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6388

double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max], // no flip

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6389

double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max])

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6420

double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6421

double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6422

double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max])

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6428

for (unsigned int n = 0; n < dml2_core_internal_bw_max; n++) { // check sdp and dram

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6452

for (unsigned int n = 0; n < dml2_core_internal_bw_max; n++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7004

double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7005

double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7023

for (bw_type = 0; bw_type < dml2_core_internal_bw_max; bw_type++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9436

for (m = 0; m < dml2_core_internal_bw_max; m++) { // check sdp and dram

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9452

for (n = 0; n < dml2_core_internal_bw_max; n++) { // check sdp and dram

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1056

double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1057

double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1155

double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1156

double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1157

double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2184

double (*urg_vactive_bandwidth_required)[dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2185

double (*urg_bandwidth_required)[dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2186

double (*urg_bandwidth_required_qual)[dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2187

double (*non_urg_bandwidth_required)[dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2188

double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2189

double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

309

double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

312

double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

316

double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

317

double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

318

double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

319

double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

320

double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

322

double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

323

double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

324

bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

562

double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

563

double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

975

double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

976

double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

977

double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

978

double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

979

double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

980

double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

983

double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

985

double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

21

case (dml2_core_internal_bw_max):