sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1258

*sw_mode = dm_sw_linear;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1005

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1035

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2757

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2772

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2800

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2826

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3331

if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3362

== dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3769

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3793

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3811

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

938

if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1065

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1095

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2830

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2845

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2873

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2899

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3438

if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3469

== dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3876

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3900

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3918

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

998

if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

245

bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

345

bool surf_linear = (tiling == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

452

if (tiling != dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

245

bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

345

bool surf_linear = (tiling == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

452

if (tiling != dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1344

if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_l_vp) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1385

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1414

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1452

if (SurfaceTiling != dm_sw_linear && PixelPTEReqHeightPTEs == 1 && ScanDirection != dm_horz) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2855

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2870

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2898

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2924

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3565

if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3596

== dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3965

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3989

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4007

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

227

bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

333

bool surf_linear = (tiling == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

444

if (tiling != dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1689

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1717

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1737

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1775

if (SurfaceTiling != dm_sw_linear && PixelPTEReqHeightPTEs == 1 && ScanDirection == dm_vert) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3092

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3105

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3518

if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3700

if (v->SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6069

if (SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6081

if (SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

171

bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

295

bool surf_linear = (tiling == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

403

if (tiling != dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1873

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1919

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1939

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1975

if (SurfaceTiling != dm_sw_linear && PixelPTEReqHeightPTEs == 1 && ScanDirection == dm_vert) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3839

if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3991

if (v->SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6705

if (SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6717

if (SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

176

bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

316

bool surf_linear = (tiling == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

422

if (tiling != dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1890

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1936

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1956

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1992

if (SurfaceTiling != dm_sw_linear && PixelPTEReqHeightPTEs == 1 && ScanDirection == dm_vert) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3419

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3432

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3932

if (v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4082

if (v->SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6795

if (SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6807

if (SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

101

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

264

bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

404

bool surf_linear = (tiling == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

510

if (tiling != dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

88

if (SurfaceTiling == dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1795

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

1915

if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2328

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2404

dml_print("DML::%s: SwModeLinear = %d\n", __func__, SurfaceTiling == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2424

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

2455

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

324

if (SurfaceTiling == dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

337

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

360

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

892

if (SurfaceTiling == dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

134

if (src->sw_mode == dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

142

if (src->sw_mode == dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

1003

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c

990

if (SurfaceTiling == dm_sw_linear) {

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

284

bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

394

bool surf_linear = (tiling == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

445

if (tiling != dm_sw_linear)

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

647

surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);

sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

684

if (pipe_src_param->sw_mode != dm_sw_linear)