sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1291

*sw_mode = dm_sw_64kb_r_x;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3341

|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

948

|| SurfaceTiling == dm_sw_64kb_r_x) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1008

|| SurfaceTiling == dm_sw_64kb_r_x) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3448

|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1125

== dm_sw_64kb_r_x))) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1160

|| TilingFormat == dm_sw_64kb_r_x) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1354

|| SurfaceTiling == dm_sw_64kb_r_x) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

3575

|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1434

if (BytePerPixelY == 2 || (BytePerPixelY == 4 && TilingFormat != dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1442

|| TilingFormat == dm_sw_64kb_r_x))

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1443

|| (BytePerPixelY == 4 && TilingFormat == dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1448

if (BytePerPixelC == 2 || (BytePerPixelC == 4 && TilingFormat != dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1456

|| TilingFormat == dm_sw_64kb_r_x))

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1457

|| (BytePerPixelC == 4 && TilingFormat == dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1622

if (BytePerPixelY == 2 || (BytePerPixelY == 4 && TilingFormat != dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1627

if ((BytePerPixelY == 8 && (TilingFormat == dm_sw_64kb_d || TilingFormat == dm_sw_64kb_d_x || TilingFormat == dm_sw_64kb_d_t || TilingFormat == dm_sw_64kb_r_x))

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1628

|| (BytePerPixelY == 4 && TilingFormat == dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1633

if (BytePerPixelC == 2 || (BytePerPixelC == 4 && TilingFormat != dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1638

if ((BytePerPixelC == 8 && (TilingFormat == dm_sw_64kb_d || TilingFormat == dm_sw_64kb_d_x || TilingFormat == dm_sw_64kb_d_t || TilingFormat == dm_sw_64kb_r_x))

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

1639

|| (BytePerPixelC == 4 && TilingFormat == dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1639

if (BytePerPixelY == 2 || (BytePerPixelY == 4 && TilingFormat != dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1644

if ((BytePerPixelY == 8 && (TilingFormat == dm_sw_64kb_d || TilingFormat == dm_sw_64kb_d_x || TilingFormat == dm_sw_64kb_d_t || TilingFormat == dm_sw_64kb_r_x))

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1645

|| (BytePerPixelY == 4 && TilingFormat == dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1650

if (BytePerPixelC == 2 || (BytePerPixelC == 4 && TilingFormat != dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1655

if ((BytePerPixelC == 8 && (TilingFormat == dm_sw_64kb_d || TilingFormat == dm_sw_64kb_d_x || TilingFormat == dm_sw_64kb_d_t || TilingFormat == dm_sw_64kb_r_x))

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

1656

|| (BytePerPixelC == 4 && TilingFormat == dm_sw_64kb_r_x)) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

369

SurfaceTiling == dm_sw_64kb_d_x || SurfaceTiling == dm_sw_64kb_r_x) {