Symbol: dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1419
pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1583
} else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1653
else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1890
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2055
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3410
if (ODMCombine == dm_odm_combine_mode_4to1 && MaxLinkBPP > 16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3799
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3809
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3811
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3819
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3821
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3828
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4102
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4116
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6221
if (MainPlaneODMCombine == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2087
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2238
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2613
myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3637
if (ODMCombine == dm_odm_combine_mode_4to1 && MaxLinkBPP > 16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3702
myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4105
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4115
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4117
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4125
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4129
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4139
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4555
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4570
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6852
if (MainPlaneODMCombine == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2105
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2256
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2632
myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3743
if (ODMCombine == dm_odm_combine_mode_4to1 && MaxLinkBPP > 16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3808
myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4195
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4205
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4207
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4215
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4219
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4229
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4643
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4658
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6943
if (MainPlaneODMCombine == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2137
if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2208
dm_odm_combine_mode_4to1) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2440
&& mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2465
== dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2492
if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
347
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1215
SurfaceRequiredDISPCLKWithODMCombineFourToOne = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_4to1,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1235
*ODMMode = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1266
*ODMMode == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1267
*ODMMode = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1298
if (ODMMode == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1640
if (ODMModeDSC == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1647
if (ODMModeNoDSC == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1733
if (ODMMode == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
752
if (MainSurfaceODMMode == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
301
if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
335
if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1925
v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;