sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1416

pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1580

if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1651

if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1336

if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

1340

&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2849

if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

2854

&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3901

locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3904

locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4002

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4192

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4215

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

4300

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1396

if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

1400

&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2922

if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

2927

&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4012

locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4015

locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4018

locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4116

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4313

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4336

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

4421

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1689

if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

1693

&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2947

if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

2952

&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4106

locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4109

locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4112

locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4210

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4407

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4430

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

4536

if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

1896

} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2058

else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

2080

} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3412

} else if (ODMCombine == dm_odm_combine_mode_2to1 && MaxLinkBPP > 32) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3795

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3802

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3814

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3824

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

3832

} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4118

} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

4147

} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

6223

} else if (MainPlaneODMCombine == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1214

unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2095

} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2241

else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2263

} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

2614

|| v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3639

} else if (ODMCombine == dm_odm_combine_mode_2to1 && MaxLinkBPP > 32) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

3703

|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4101

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4108

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4120

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4135

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4143

} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4572

} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

4601

} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

6854

} else if (MainPlaneODMCombine == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1086

unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2113

} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2259

else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2281

} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

2633

|| v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3745

} else if (ODMCombine == dm_odm_combine_mode_2to1 && MaxLinkBPP > 32) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

3809

|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4191

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4198

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4210

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4225

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4233

} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4660

} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

4689

} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c

6945

else if (MainPlaneODMCombine == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1173

unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2140

} else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2206

dm_odm_combine_mode_2to1 &&

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2435

&& mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2469

== dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

2499

} else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

351

else if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1212

SurfaceRequiredDISPCLKWithODMCombineTwoToOne = dml32_CalculateRequiredDispclk(dm_odm_combine_mode_2to1,

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1247

*ODMMode = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1271

*ODMMode = dm_odm_combine_mode_2to1;

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1300

else if (ODMMode == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1642

else if (ODMModeDSC == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1649

else if (ODMModeNoDSC == dm_odm_combine_mode_2to1)

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

1737

} else if (ODMMode == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

755

} else if (MainSurfaceODMMode == dm_odm_combine_mode_2to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

301

if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

335

if (dst->odm_combine == dm_odm_combine_mode_2to1 || dst->odm_combine == dm_odm_combine_mode_4to1) {

sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

337

unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4);

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1921

v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;