Symbol: dm_420
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
501
input->dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1509
pipes[pipe_cnt].dout.output_format = dm_420;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1777
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3196
if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
322
if (pixelFormat == dm_n422 || pixelFormat == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3228
if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3250
} else if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
371
if (pixelFormat == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3903
} else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4171
|| (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4184
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
537
if (OutputFormat == dm_420 || (InterlaceEnable && ProgressiveToInterlaceUnitInOPP))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1813
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3270
if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3302
if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3357
} else if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
346
if (pixelFormat == dm_n422 || pixelFormat == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
395
if (pixelFormat == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4017
} else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4292
|| (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4305
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
529
if (OutputFormat == dm_420 || (Interlace && ProgressiveToInterlaceUnitInOPP))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1769
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3276
if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3308
if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3363
} else if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4111
} else if (locals->HActive[k] > DCN21_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4386
|| (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4399
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
517
if (pixelFormat == dm_n422 || pixelFormat == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
566
if (pixelFormat == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
746
if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && ProgressiveToInterlaceUnitInOPP))
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2047
if (v->OutputFormat[k] == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3378
if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3818
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN30_MAX_FMT_420_BUFFER_WIDTH
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4093
|| (v->OutputFormat[k] == dm_420 && v->Interlace[k] == true && v->ProgressiveToInterlaceUnitInOPP == true))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
663
if (pixelFormat == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
688
if (pixelFormat == dm_420 || pixelFormat == dm_444 || pixelFormat == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
716
if (pixelFormat == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
924
if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && v->ProgressiveToInterlaceUnitInOPP))
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1009
if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2230
if (v->OutputFormat[k] == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3604
if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4124
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN31_MAX_FMT_420_BUFFER_WIDTH
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4542
if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
692
if (pixelFormat == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
717
if (pixelFormat == dm_420 || pixelFormat == dm_444 || pixelFormat == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
745
if (pixelFormat == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1027
if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2248
if (v->OutputFormat[k] == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3710
if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4214
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN314_MAX_FMT_420_BUFFER_WIDTH
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4629
if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
710
if (pixelFormat == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
735
if (pixelFormat == dm_420 || pixelFormat == dm_444 || pixelFormat == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
763
if (pixelFormat == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2357
== dm_420 && mode_lib->vba.Interlace[k] == 1 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2454
if (mode_lib->vba.OutputFormat[k] == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
339
if (mode_lib->vba.OutputFormat[k] == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
118
if (pixelFormat == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1259
if (OutFormat == dm_420 && HActive > DCN32_MAX_FMT_420_BUFFER_WIDTH &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1276
if (Output == dm_hdmi && OutFormat == dm_420 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1600
if (Format == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3591
if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
56
if (pixelFormat == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
79
if (pixelFormat == dm_420 || pixelFormat == dm_444 || pixelFormat == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
1284
if (e2e_pipe_param->dout.output_format == dm_420)